Lorenzo Ciampolini

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI

This work presents a method for the design and characterization of a scalable ultra-wide voltage range static random access memory using an optimized 10 transistor bitcell, targeting minimum operating voltage, high yield and a Silicon-CAD correlation within 5%. The method is based on both static and dynamic metrics. The experimental validation was first performed in BULK CMOS 65 nm on a 32 kb memory array, then applied in 28 nm FDSOI on a 64 kb memory array. Over 10× energy reduction is achieved across a wide voltage range, i.e., from 1.2 V to 0.35 V while achieving high speed at the nominal voltage, i.e., 485 MHz in 65 nm BULK and 1 GHz in 28 nm FDSOI.

Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell

The tendency for low energy consumption in systems-on-chip results in a need for memories operating in the near- and sub-threshold regions. This paper gives a comparative study of Static Random Access Memory (SRAM) bitcells working under Ultra-Low Voltage in 32nm CMOS. A new 10T SRAM bitcell is then proposed and features low leakage current. It is capable of operation under ULV (~300mV) and allows bit-interleaving technique that is critical to cope with multiple bit soft-errors for reducing dynamic and static power consumption compared to state-of-the-art bitcells.

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

We present a design and characterization method for a scalable ultra-wide voltage range (UWVR) SRAM bitcell array, targeting a minimum voltage prediction, high yield and Si-CAD correlation within 5%. The experimental validation is first performed in bulk CMOS 65nm, then confirmed in 28nm FDSOI. Over 10× energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.

Electrical characterization and compact modeling of MOSFET body effect

In this paper we report on the impact of the depth dopant profile on MOSFETs threshold voltage shifts induced by bulk biases. This body effect is characterized with an original procedure using experimental data, but also a series of TCAD simulations, including advanced process simulation of the dopant distribution along the depth of the transistor. Finally the impact of the doping profile non-uniformity on the body effect is accounted for within the framework of a charge sheet model.

Dynamic single-p-well SRAM bitcell characterization with back-bias adjustment for optimized wide-voltage-range SRAM operation in 28nm UTBB FD-SOI

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120μm2) single p-well (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. The results from a 140kb programmable dynamic SRAM characterization test module provide both information about location and cause of failures as well as power and performance by mimicking system operating conditions over a wide supply voltage range. A 410mV minimum operating voltage and less than 310mV data retention voltage with a leakage current close to 100fA/bitcell are measured. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells

We consider the general problem of the efficient and accurate determination of the yield of an integrated circuit, through electrical circuit level simulation, under variability constraints due to the manufacturing process. We demonstrate the performance of our general-purpose Importance Sampling based algorithm for the case of an industrial SRAM application. Section 1 reviews the notions of yield and how this translates to very low probability of failure estimation. We explain in detail the working principle of statically and dynamically write-assisted SRAM bitcells and the limitations of the classical static approximations for yield estimation of these structures. Section 2 explores naïve statistical approaches for the determination of low probabilities and the notion of variance reduction. Section 3 explains the detailed mathematical background of our new algorithm. We show how the original extremely challenging problem is translated to a simpler convex optimization problem, and how the algorithm produces a standard confidence interval associated to a probability or quantile. Section 4 presents the quantitative results and speedup factors obtained on an industrial SRAM bitcell for the analysis of a write failure mechanism. Results obtained on static negative bit line assisted SRAM compares favorably to results obtained with extrapolation of static models and prove the accuracy of the method, while results obtained on dynamic negative bit line assisted SRAM allow to quantitatively optimize the assist circuitry and help to reduce its over-design margins.

A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI

In this study, a 128 kb ultra low voltage (ULV) SRAM, based on a 7T bitcell with one bitline, is presented. Overall energy efficiency is enhanced by optimizations on all abstraction levels, i.e., from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. The minimum operating voltage VMIN is measured as 240mV and the retention voltage is found at 200mV.

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

This work investigates the effects of process variability on the dynamic stability of a 6-Transistor Static Random Access Memory bitcell manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) technology node. The study is carried out for two different well architectures: single-well (peculiar to UTBB-FDSOI) and dual-well (like in standard CMOS), through Most-Probable Failure Point tracking methodology coupled with Importance Sampling. Different failure mechanisms appearing under different operating conditions are discussed. We show that the Read-After-Write failure criterion based on multiple Word-Line pulses is the most accurate way to evaluate bitcell failure rate and thus its yield under realistic dynamic conditions. The methodology exposed in this work is applied to demonstrate the superior properties of the single-well architecture.

UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM

This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6-Transistor Single-P-Well Static Random Access Memory (6T-SRAM) in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. RTS noise impact is observed through Write-Ability measurements on a 143Kb SRAM macro. A SPICE-level bias- and time-dependent RTS model peculiar to UTBB FD-SOI, introducing the back-gate as a second RTS noise source and considering the front- and back-gate coupling, is used for simulations to confirm silicon observations. It is shown that the body-biasing feature of UTBB FD-SOI does not introduce critical RTS noise compared to the one originated from the device front gate.

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI

This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6 Transistors single P-well Static Random Access Memory (6T-SRAM) manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. A SPICE-level bias-and time-dependent RTS model peculiar to UTBB FD-SOI, which considers both front- and back-gate of the device as RTS sources, is presented. The Bit-Error-Rate is evaluated on silicon dies through the write-ability (WA) failure criterion and with a dedicated back-biasing strategy. Simulations evidence the role of RTS-induced dynamic variability with respect to process variability and show a good agreement with measurements.