Lorenzo Pieralisi

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

Reconfigurable architectures and NoC (Network-on- Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design. On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price < 10% in area in power consumption with respect to the overall system.

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC

Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On the other hand, ASIC designs suffer from skyrocketing manufacturing costs and long development cycles. This results in an increasing need for postfabrication programmability at both software and hardware levels. FPGAs provide maximum flexibility with their fine-grained architecture but bring severe overhead in timing, area, and power consumption. Wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance with software flexibility.1 Their coarser granularity reduces area, delay, power consumption, and reconfiguration time, but they introduce trade-offs in processing-element design.

The MORPHEUS Data Communication and Storage Infrastructure

The previous chapter described the most significant blocks that compose the MORPHEUS architecture, and the added value they provide to the overall com- putation efficiency and/or usability. The present chapter describes the way that the memory hierarchy and the communication means in MORPHEUS are organized in order to provide to the computational engines the necessary data throughput while retaining ease of programmability. Critical issues are related to the definition of a computation model capable to hide heterogeneity and hardware details while providing a consistent interface to the end user. This model should be complemented by a data storage and movimentation infrastructure that must sustain the bandwidth requirements of the computation units while retaining a sufficient level of programmability to be adapted to all the different data flows defined over the architecture in its lifetime. These two aspects are strictly correlated and their combination represents the signal processor interface toward the end-user. For this reason, in the following, a significant focus will be given to the definition of a consistent computation pattern. This pattern should enable the user to confront MORPHEUS, in its strong heterogeneity, as a single computational core. All design options in the definition of the Memory hierarchy and the interconnect strategy will be then derived as a consequence of the theoretical analysis that underlines the computational model itself.