Lori D. Washington

Exploring the limits of stress-enhanced hole mobility

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (/spl mu/RS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Leakage Current Control in Recessed SiGe Source/Drain Junctions

The impact of different process parameters, namely, the trench etch depth, the total epitaxial SiGe thickness, and the epi elevation, on the leakage current of recessed Si 0.8 Ge 0.2 source/drain junctions has been systematically investigated. Besides the behavior of the forward and the reverse currents, attention is also given to the temperature dependence of the leakage current. It is found that both the bulk and the peripheral leakage current density increase strongly with increasing etch depth. Empirically, an exponential dependence has been observed between the area leakage current density at - 1 V and the distance d j between the Si 0.8 Ge 0.2 -Si interface and the electrical p-n junction, whereby an increase by 1 dec for every 43 nm of reduction in d j occurs. This can be understood by the fact that the responsible defects originate mainly at the SiGe-Si interface. The perimeter current density shows for certain process splits an exponential dependence on the total thickness of the epitaxial layer t SiGe , with an increase by a decade for every 50 nm increase in thickness. Also, the generation and recombination lifetimes have been studied in order to determine an effective energy level of the electrically active defects.

Impact of Etching Depth on the Leakage Current of Recessed SiGe Junctions

Here, a systematic study is made of the leakage current in huge-area SiGe-Si p+-n junctions. As will be shown, both the perimeter and area leakage current density are a sensitive function of the S/D etch depth, whereby a higher leakage is obtained for deeper trenches. This can be explained by the presence of dislocations at the SiGe-Si interface, as revealed by transmission electron microscopy (TEM) and their relative distance to the electrical junction

Diode Analysis of Electrically Active Defects in Recessed SiGe Source/Drain Diodes

M. Bargallo Gonzalez, G. Eneman, P. Verheyen, C. Claeys, A. Benedetti, H. Bender, K. De Meyer, E. Simoen, R. Schreutelkamp, L. Washington and F. Nouri IMEC, Kapeldreef 75, B-3001 Leuven, Belgium Ph:32 16 281381, enemang@imec.be ESAT-INSYS, KU Leuven, Kasteelpark Arenberg 10, 3001 Heverlee, Belgium Research assistant of The Fund for Scientific Research – Flanders, Belgium Applied Materials Inc, Sunnyvale, CA, USA