Faran Nouri

Exploring the limits of stress-enhanced hole mobility

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (/spl mu/RS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

A thermo-mechanical stress model (TMS) is presented to explain the impact of sub-melt laser anneal (LA) on SiON dielectric and on the overall transistor performance. An Lgmin reduction of 15nm/5nm for nMOS/pMOS over our poly-Si/SiON reference, with 8% capacitance and 10% source and drain resistance (RSD) improvement, is demonstrated. Best device performance and NBTI immunity are reached by lowering the laser power and optimizing the nitrogen and fluorine profile. This minimizes the increase of Si dangling bonds at the SiON/Si interface and the oxide fixed charges, generated by the thermo-mechanical stress (TMS) during the LA fast thermal gradient. The full potential of LA is demonstrated by skipping the RTA. An Lgmin gain of 25nm/20nm is achieved for metal gate nMOS/FUSI gate pMOS devices over the junction RTA reference. Optimal 0.26 fF/mum overlap capacitance values (at Vdd= | 1 | V), 18%/ 23% for nMOS/pMOS lower CV/I product and pMOS improved RSD are demonstrated

Leakage Current Control in Recessed SiGe Source/Drain Junctions

The impact of different process parameters, namely, the trench etch depth, the total epitaxial SiGe thickness, and the epi elevation, on the leakage current of recessed Si 0.8 Ge 0.2 source/drain junctions has been systematically investigated. Besides the behavior of the forward and the reverse currents, attention is also given to the temperature dependence of the leakage current. It is found that both the bulk and the peripheral leakage current density increase strongly with increasing etch depth. Empirically, an exponential dependence has been observed between the area leakage current density at - 1 V and the distance d j between the Si 0.8 Ge 0.2 -Si interface and the electrical p-n junction, whereby an increase by 1 dec for every 43 nm of reduction in d j occurs. This can be understood by the fact that the responsible defects originate mainly at the SiGe-Si interface. The perimeter current density shows for certain process splits an exponential dependence on the total thickness of the epitaxial layer t SiGe , with an increase by a decade for every 50 nm increase in thickness. Also, the generation and recombination lifetimes have been studied in order to determine an effective energy level of the electrically active defects.

Model to predict gate tunneling current of plasma oxynitrides

Two key parameters for silicon MOSFET scaling, equivalent oxide thickness (EOT) and gate leakage current density (J/sub g/) are measured and modeled for silicon oxynitride (Si-O-N) gate dielectrics formed by plasma nitridation of SiO/sub 2/. It is found that n-MOSFET inversion J/sub g/ is larger than p-MOSFET inversion J/sub g/ when the gate dielectric consists of less than 27% nitrogen atoms, indicating substrate injection of electrons is dominant for this range of plasma nitrided Si-O-N. To examine the intrinsic scaling of Si-O-N, we model EOT and n-MOSFET J/sub g/ for sub-2-nm physically thick gate dielectrics as a function of film physical thickness and nitrogen content. The model has four free fitting parameters and unlike existing models does not assume a priori the values of the oxide and nitride dielectric constant, barrier height, or effective mass. It indicates that at a given EOT, leakage current of n-MOSFETs with Si-O-N gate dielectrics reaches a minimum at a specific nitrogen content. Through the use of this model, we find that plasma nitrided Si-O-N can meet the 65-nm International Technology Roadmap for Semiconductors specifications for J/sub g/, and we estimate the nitrogen concentration required for each node and application.

Physical models for predicting plasma nitrided Si-O-N gate dielectric properties from physical metrology

Using simple physical models, specific relationships between parameters measured by X-ray photoelectron spectroscopy (XPS) and those measured on MOS transistors are described for silicon oxynitride gate dielectrics prepared by plasma nitridation. Correlations are established between the equivalent oxide thickness (EOT) and gate leakage current and the nitrogen anneal dose and physical thickness as measured by XPS. These correlations, from devices in the 10 to 13 /spl Aring/ EOT range, allow accurate estimates of electrical thickness and leakage without device fabrication, enabling both development and process monitoring for sub-130-nm node gate dielectrics.

The evaluation of performance parameters of MOSFETs with alternative gate dielectrics

This brief discusses a benchmarking methodology for the evaluation of performance parameters (g/sub mmax/ and I/sub dsat/) of MOSFETs with alternative gate dielectrics. It is shown that assuming ideal scaling for either or with electrical oxide thickness (g/sub mmax/ or I/sub dsat/ /spl prop/ T/sub oxinv//sup -/spl alpha// with /spl alpha/ = 1) instead of using experimental scaling trends for a baseline dielectric results in unrealistically pessimistic conclusions about the performance of alternative gate dielectrics. Factors In addition to mobility reduction which can contribute to sub-ideal scaling (/spl alpha/ < 1) for any dielectric are discussed. This bench marking methodology for performance evaluation is demonstrated for oxynitride gate dielectric films with equivalent oxide thickness (EOT) approaching 11 /spl Aring/.

Dissolution of extended defects in strained silicon

The experimental and theoretical analyses performed in this work provide an insight into the impact of external stress on extended defects that form in silicon after ion implantation. It is shown experimentally that the embedded SiGe source/drain regions help to dissolve the extended defects in the adjacent silicon. The reduced amount of free and clustered interstitials is known to reduce junction leakage and increase dopant activation. These benefits are expected to improve further for the subsequent technology generations, due to the shrinking distance between the source and drain SiGe regions. A quantitative model of defect evolution in silicon with embedded SiGe is proposed. The model can be applied to optimize the combination of stress engineering, implant conditions, and thermal budget for the best device performance.