Loris Vendrame

Charge-based on-chip measurement technique for the selective extraction of cross-coupling capacitances

We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) that enables the selective extraction of cross-coupling capacitance between arbitrary on-chip interconnects. We discuss the silicon implementation on a 0.18um CMOS process and report preliminary experimental results. The accurate characterization of wiring capacitance is a key task in the design and validation of deep sub micron (DSM) integrated circuits because of the growing impact of interconnects on performance, power and reliability. There are three main ways for characterizing wiring capacitances: i) parameter extraction from a 3D model derived from layout, ii) indirect measure by means of parametric model fitting, and iii)

Crosstalk-based capacitance measurements: theory and applications

Geometry scaling increases the relative effect of coupling capacitances on performance, power, and noise so that they need to be carefully taken into account during process development, characterization, and monitoring. In the last decade, charge-based capacitance measurements (CBCMs) have been widely used to estimate on-chip wiring and coupling capacitances because of their accuracy and simplicity. We provide a thorough theoretical and experimental study of CBCMs applied to the selective extraction of cross-coupling capacitances. We take a historical perspective starting from the original CBCM approach proposed by Chen in 1996, and we present a new technique for crosstalk-based capacitance measurements (CTCMs). CTCMs improve the accuracy and usability of CBCMs while reducing the complexity of the test structures. We present the theory of CTCM, we provide experimental results demonstrating its improved accuracy, and we discuss its application to a wide range of process monitoring and testing tasks. Experimental results are used throughout the paper to support the discussion.

Spacing impact on MOSFET mismatch

Many test structures embedded in various technologies were measured to study the spacing impact on MOSFET mismatch. This impact is showed to highly depend on technology, device family, device type and bias conditions. The study of spatial correlation allows to properly model spacing impact on mismatch: this analysis -in this paper focused on MOSFETs- may be extended to any device. Finally, a worst case model that only requires standard matched pairs at minimum spacing is proposed to provide designers the maximum matching degradation that may affect spaced devices.

A new test structure for measuring on-chip cross-coupling capacitances

We present a new test structure for measuring on-chip cross-coupling capacitance by means of crosstalk-induced supply currents. The key advantage of the proposed approach over existing charge-based capacitance measurements (CBCMs) based on cross talk is that the victim line is kept at a constant voltage level, thus avoiding short-circuit currents and enabling complete compensation of charge redistribution effects. We present preliminary experimental results obtained from a 0.13 /spl mu/m CMOS implementation.

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.

New applications of cross-talk-based capacitance measurements [CMOS ICs]

Charge-based capacitance measurements (CBCMs) are widely used to estimate on-chip wiring capacitances because of their accuracy and simplicity. Enhanced CMOS transducers for CBCM have been recently proposed that exploit cross-talk to selectively measure cross-coupling capacitances. In this paper, we propose two new applications of cross-talk-based capacitance measurements: mismatch measurement of stacked metal-metal capacitor pairs, and localization of wire interruptions. We present the measurement techniques, we discuss their implementation and we report preliminary experimental results.

A modular test structure for CMOS mismatch characterization

In this work a new test structure for mismatch characterization of CMOS technologies is presented. The test structure is modular, with a reduced area and it can be inserted in the space between the dies (scribe lines) on the wafers. The test structure has been implemented in a standard 0.18-/spl mu/m digital CMOS technology.

A new methodology for the statistical analysis of VLSI CMOS circuits and its application to flash memories

In this paper a new CAD methodology for the statistical analysis of VLSI CMOS circuits is presented. A novel very accurate position-dependent mismatch model has been implemented into a complete CAD tool. The tool is fully integrated in an environment of commercial tools and it has been experimented on in the Flash Memory CAD Group in STMicroelectronics. As an example of application, a bandgap test circuit has been considered and the results have been compared with experimental data. This methodology has also been applied to the read path of a complex flash memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the accuracy of the proposed simulation flow and models.

Statistical methodologies for integrated circuits design

The continuous scaling of physical dimensions has strongly increased circuit performance variability and the traditional corner-case methodology is becoming unreliable. As a consequence, there is an urgent need for new and more accurate statistical models. In this scenario, the purpose of this paper is twofold: 1) to give the reader the basic concepts of statistical modeling, and 2) to discuss a viable statistical approach that could be adopted into a traditional IC design flow for the next technology generations.

Time domain approach for the evaluation of RC delays effects in ULSI interconnect lines

The evaluation of RC effects in ULSI technology is important both for process development and for accuracy verification of back-end modeling and cad-tools. The paper proposes a new methodology with one possible implementation for the measurement of RC delays in ULSI interconnect lines (DUT). The proposed implementation has been developed at wafer level by means of a mid-complexity test circuit whose working principle is based on the comparison between the RC delay of the DUT and a well-known reference delay generated on-chip.