Lounis Kessal

Efficient ASIC and FPGA implementations of IIR filters for real time edge detection

To reduce the computation cost, Deriche (1987, 1990) extended the work from Canny (1986) on optimal edge detectors to the use of recursive filters. Nevertheless, this cost is still too high for real time implementation on FGGA circuits. Here, we optimized both the algorithmic and architectural aspects of the original Deriche filter. A new organization of the filter is proposed at the 2D and 1D levels which reduces the memory size and the computation cost by a factor of two for both software and hardware implementations. We prove that the use of only 3 bits to code the scale parameter does not reduce the quality. The result from this choice is that the first order recursive filter which is the basic block of the entire architecture can be built with only 4 adders. The architecture of a 10 Mpixels/second filter on an unique FPGA is described.

Evaluation of edge detectors performances with a discrete expression of Canny's criteria

Three quality criteria have been defined by Canny (1986) to deduce an optimal edge detector in the continuous space domain. In this paper, we give an equivalent for these criteria in the discrete space domain. These new criteria are better in accordance with experimental results than previous one. Furthermore, they are more suitable to compare filters performances. We explain how to compute them. We compare some edge detectors. Finally, we use them to prove the qualities of a new simpler implementation of a second order recursive smoothing filter issued from Cannys theory.

How to use high speed reconfigurable FPGA for real time image processing

In France, ten research teams study and build a hardware architecture (ARDOISE) which is dedicated to real time image processing. This architecture uses fast or dynamic reconfiguration allowed by new FPGA circuits. During a video frame duration, several algorithms are computed sequentially on the same hardware. This paper highlights the architectural concepts used to build ARDOISE. Then an analytical model is defined in order to complete the limits and the performances expected in the use of the dynamic reconfiguration scheme. An example in image segmentation is developed to show a possible partitioning methodology.

Dataflow programming model for reconfigurable computing

This paper addresses the problem of image processing algorithms implementation onto dynamically and reconfigurable architectures. Today, these Systems-on-Chip (SoC), offer the possibility to implement several heterogeneous processing elements in a single chip. It means several processors, few hardware accelerators as well as communication mediums between all these components. Applications for this kind of platform are described with software threads, running on processors, and specific hardware accelerators, running on hardware partitions. This paper focuses on the complex problem of communication management between software and hardware actors for dataflow oriented processing, and proposes solutions to leverage this issue.

Real-time image processing with dynamically reconfigurable architecture

Abstract During the last few years, many architectures using processors and/or field programmable gate arrays (FPGA) were built to accelerate computationally complex problems. The processors allow a high degree of flexibility, whilst the FPGA implementation might be considerably faster. In spite of the possibility of reconfiguring the conventional FPGA an unlimited number of time, many of these architectures were built to compute a single application. If the FPGA is reconfigured several times to execute various algorithms, the configuration time increases and degrades global performances. In this paper, an architecture dedicated to real-time image processing using the AT40K reconfigurable FPGA family is presented (ARDOISE project 1 ). We discuss Dynamic Reconfiguration (or Run-Time Reconfiguration), a technique based on the reuse of the same device (an FPGA configured on the fly) by scheduling the execution of different algorithms building an application. The techniques and the tools developed to test and use the system are described.

Reconfigurable hardware for real time image processing

Nowadays, a new technology can provide both advantages of ASIC: speed and of parallel processors: flexibility, with limited inconvenience. It is based on dynamically configurable FPGA. These devices can be totally or partially configured in less than 1 ms and their processing speed is approximately 1/3 of the ASIC speed. We present the ARDOISE reconfigurable architecture. The successive algorithms which must be applied sequentially to an input image in real time are swapped on the same FPGA hardware inside the frame duration. The choice of the algorithms can be made in real time and data dependent. In the second section, we discuss the limits on the usefulness of dynamical reconfiguration and give an estimation of the performances in term of silicon reduction. The third section presents an application for real time image segmentation programmed on ARDOISE. In this example, we show that 4 algorithms which use 7 configurations can be applied in real time on images of 512/spl times/512 pixels every 40 ms.

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications

Recent FPGAs allow the design of efficient and complex Heterogeneous Systems-on-Chip (HSoC). Namely, these systems are composed of several processors, hardware accelerators as well as communication media between all these components. Performances provided by HSoCs make them really interesting for data-flow applications, especially image processing applications. The use of this kind of architecture provides good performances but the drawback is an increase of the programming complexity. This complexity is due to the heterogeneous deployment of the application on the platform. Some functions are implemented in software to run on a processor, whereas other functions are implemented in hardware to run in a reconfigurable partition of the FPGA. This article aims to define a programming model based on the Synchronous Data-Flow model, in order to abstract the heterogeneity of the implementation and to leverage the communication issue between software and hardware actors.

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.

FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLA

In this paper, we describe the implementation on Field Programmable Gate Array (FPGA) of generic platform for a Bio-Inspired Medical Hearing Aid (BIMHA). The rapid growth in the industrial technologies has participated in the development of several and performed hardware systems for digital signal processing applications. In spite of the fast emergence of the new micro and nanotechnologies, the most recent digital hearing aids do not still succeed in satisfying the hearing-impaired people. These hearing prosthesis use hardware as solution to correct the deficiency for impaired persons. But, for the same degree of hearing deficiency, the pathology of the hearing impaired persons could be different which explains the no satisfaction of deaf people using hearing prosthesis. It is in this perspective that the large number of studies and applications were oriented to the signal and speech processing rather than in purely hardware technological solutions. In order to contribute for the amelioration of intelligibility and the hearing comfort quality, we propose a new approach using Discrete Wavelet Transform and Over-Lap and Add technique (DWT-OLA). Our aim is to keep small device sizes and reduced power consumption in one side and in the other side, to enhance speech by denoising, echo-cancelling and frequency shifting. We conducted experiments on speech data taken from arctic corpus and evaluated the system performance using MSE and SNR for objective measurements and Mean Opinion Score (MOS) for subjective ones. We obtained a gain of intelligibility reaching 70%. Moreover, the proposed FPGA platform involves fewer resources, reduced memory-size and les power consumption as compared to some previous designs.

Fast Recursive Implementation of the Gaussian Filter

On one hand, the convolution with the truncated impulse response (ir) of Gaussian filters leads to a high computation cost when the standard deviation a of the Gaussian increases. On the other hand, recursive filters that approximate the Gaussian filters reduce the computation cost but can only be applied to finite length signals due to the infinity of the ir on both sides.