Sébastien Pillement

Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments.

DART: a functional-level reconfigurable architecture for high energy efficiency

Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13u2009m CMOS SoC implementing a specialized DART cluster is presented.

OveRSoC: a framework for the exploration of RTOS for RSoC platforms

This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded Real Time Operating Systems (RTOSs) for Reconfigurable System-on-Chip-based platforms.Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution of OS services on this kind of platform. The experimental results show that our components accurately model the dynamic and deterministic behavior of both application and RTOS.

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

This paper presents the implementation of the coarse-grained reconfigurable architecture (CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison. These low-cost hardware techniques would allow to tolerate temporary faults (including so called soft errors caused by radiation), provided that some technique based on re-execution of the last operation is used. Synthesis results obtained for a 90nm CMOS technology have confirmed significant hardware and power consumption savings of the proposed approach over commonly used duplication with comparison. Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design.

An energy-efficient ternary interconnection link for asynchronous systems

We introduce a new ternary link including a binary-to-ternary encoder and a ternary-to-binary decoder in voltage-mode multiple-valued logic (MVL). This link improves the transistor count compared to existing designs and it has no DC current path. The complete link was simulated with SPICE and a 0.13mum CMOS technology. It additionally shows interesting advantages on power consumption for global interconnects compared to full-swing signaling binary systems (up to 56.4% less energy consumption). Its low propagation delay is also an advantage in the design of high-speed on-chip links for asynchronous systems

A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources

This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded real time operating systems for reconfigurable System-On-Chip based platforms. Here, we describe the overall methodology and the corresponding design environment. The method is based on abstract and modular SystemC models that allow to explore, simulate, and validate the distribution of OS services on this kind of platform. The experimental results show that our components accurately model the dynamic and deterministic behaviour of RTOS while demonstrating flexible properties.

Fault-aware configurable logic block for reliable reconfigurable FPGAs

Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, todays FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove only the upsets affecting the configuration bitstream, unfortunately, there are other sources of faults that might directly affect hardware resources of reconfigurable FPGAs. Their nature and consequences differ from those which occur in the configuration bitstream and their effects cannot be corrected by performing configuration writeback. This paper proposes a fault-aware configurable logic block architecture to detect such faults in FPGA-implemented logic circuits. The fault coverage of the proposed architecture is also discussed. Hardware complexity estimations suggest higher efficiency of the approach proposed over similar existing ones.

A robust cooperative spectrum sensing method against faulty nodes in CWSNs

Cognitive wireless sensor networks (CWSNs) become promising infrastructures, which can improve spectrum utilization of traditional wireless sensor networks (WSNs). For cognition in WSNs, spectrum sensing is one of the most crucial function to prevent hazardous interferences with the licensed users and to identify available spectrum for improving the spectrum utilization. In this paper, we propose a robust cooperative spectrum sensing method based on Dempster-Shafer (D-S) theory. Firstly, taking into account the increase of transmitted data with the rise of the number of sensor nodes and the power limitation of nodes, we propose to adapt the D-S theory to the binary hypothesis test at the local sensing sensor node, in order to reduce the amount of control data to be transmitted. Secondly, we consider that some cognitive nodes may not work as expected. Hence, facing this problem of faulty nodes in CWSNs, we propose an evaluation method which considers simultaneously the sensor node reliability and the mutually supportive degree among different sensor nodes to support adapted decision. Simulation results show that the proposed method allows to improve significantly the detection performance compared to other techniques, even in presence of faulty nodes.

FlexTiles: a globally homogeneous but locally heterogeneous manycore architecture

This paper introduces the FlexTiles platform, which consist of a manycore architecture associated with a complete tool flow. The different components of the manycore architecture are based on general purpose processors (GPP), low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. Thus, in order to mask the underlying heterogeneity of such an architecture, innovative software mechanism and hardware interface were defined. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. In order to facilitate the architecture adaptation under different scenarios, a programming model that considers both static and dynamic behaviors is proposed. The proposed architecture has been implemented on a FPGA platform and has shown the validity of the proposed solution.

Hardware runtime verification of embedded software in SoPC

This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a micro-controller and a FPGA. The goal is to verify at runtime that the execution of the software on the micro-controller conforms to a set of properties. To do so, a minimal instrumentation of the software is used to send events to a set of monitors implemented in the FPGA. These monitors are synthesised from a formal specification of the expected behavior of the system expressed as a set of past-time linear temporal logic (ptLTL) formulas.