Lourdes Miro-Amarante

A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach

This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11141, and a system clock frequency of 27 MHz.

Real time multiple objects tracking based on a bio-inspired processing cascade architecture

This paper presents a cascade architecture for bio-inspired information processing. We use AER (Address Event Representation) for transmitting and processing visual information provided by an asynchronous temporal contrast silicon retina. Using this architecture, we also present a multiple objects tracking algorithm; this algorithm is described in VHDL and implemented in a FPGA (Spartan II), which is part of the USB-AER platform developed by some of the authors.

Live demonstration: Real time objects tracking using a bio-inspired processing cascade architecture

This demonstration shows how a new bio-inspired processing cascade architecture is used for simultaneous objects tracking. This demonstration is associated with Event-based Neuromorphic Systems track.

A spiking neural network for real-time Spanish vowel phonemes recognition

This paper explores neuromorphic approach capabilities applied to real-time speech processing. A spiking recognition neural network composed of three types of neurons is proposed. These neurons are based on an integrative and fire model and are capable of recognizing auditory frequency patterns, such as vowel phonemes; words are recognized as sequences of vowel phonemes. For demonstrating real-time operation, a complete spiking recognition neural network has been described in VHDL for detecting certain Spanish words, and it has been tested in a FPGA platform. This is a stand-alone and fully hardware system that allows to embed it in a mobile system. To stimulate the network, a spiking digital-filter-based cochlea has been implemented in VHDL. In the implementation, an Address Event Representation (AER) is used for transmitting information between neurons.

LVDS Serial AER Link performance

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows analysing a LVDS serial AER link produced by a Spartan 3 FPGA, or by a commercial LVDS transceiver. The interface allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.

Image convolution using a probabilistic mapper on USB-AER board

In this demo we propose a method for computing real time convolution on AER images. For that we use signed events. The AER events produced on an AER retina or an image/video to AER conversor, are processed using a probabilistic multi event mapper that produces more than one event for each incoming event according to an assigned probability. Kernel convolution size are limited by mapping tables size (on board RAM) and AER bus bandwidth. On reconstruction signed events needs to be simplified (subtracted) to get final convolved image. For that two different methods are proposed.

A LVDS Serial AER Link

Address-event-representation (AER) is a communication protocol for transferring asynchronous events between VLSI chips, originally developed for bio-inspired processing systems (for example, image processing). Such systems may consist of a complicated hierarchical structure with many chips that transmit data among them in real time, while performing some processing (for example, convolutions). The event information is transferred using a high speed digital parallel bus (typically 16 bits and 20ns-40ns per event). This paper presents a testing platform for AER systems that allows to analyse a LVDS Serial AER link. The interface allows up to 0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that the platform could support 1.2 Gbps.

Semi-wildlife gait patterns classification using statistical methods and Artificial Neural Networks

Several studies have focused on classifying behavioral patterns in wildlife and captive species to monitor their activities and so to understanding the interactions of animals and control their welfare, for biological research or commercial purposes. The use of pattern recognition techniques, statistical methods and Overall Dynamic Body Acceleration (ODBA) are well known for animal behavior recognition tasks. The reconfigurability and scalability of these methods are not trivial, since a new study has to be done when changing any of the configuration parameters. In recent years, the use of Artificial Neural Networks (ANN) has increased for this purpose due to the fact that they can be easily adapted when new animals or patterns are required. In this context, a comparative study between a theoretical research is presented, where statistical and spectral analyses were performed and an embedded implementation of an ANN on a smart collar device was placed on semi-wild animals. This system is part of a project whose main aim is to monitor wildlife in real time using a wireless sensor network infrastructure. Different classifiers were tested and compared for three different horse gaits. Experimental results in a real time scenario achieved an accuracy of up to 90.7%, proving the efficiency of the embedded ANN implementation.