Luan Jing-En

Numerical and Experimental Study of Interface Delamination in Flip Chip BGA Package

The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.

Characterization of silicon die strength with application to die crack analysis

After encapsulation, thermo-mechanical deformation builds up within the electronic packages due to temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. As the trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, they bring challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. One of the reliability problems, die crack, becomes more serious due to the larger die area compared with package size, thinner thickness and thermal mismatch between the respective materials within the package. Die strength can be adversely affected during various manufacturing processes, such as grinding and chipping. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work try to find the simple test method for determination of die strength to improve the scatter and try to differentiate the factors that affect the variability of die strength, in order to find out the causes of the weakness of the die strength. The surface conditions (roughness) of the specimens are determined by atomic force microscopy (AFM) and correlated to failure strength. A practical example is presented here that die cracking analysis has been done for a chip array thin core BGA (CTBGA) during thermal cycling. The die stress is calculated based on the finite element analysis (FEA) of CTBGA and the FEA-predicted die stress is used to predict the die failure rate compared with the experiment results.

Analysis of interfacial delamination in IC packaging: Use stress or fracture mechanics?

After encapsulation, thermo-mechanical deformation builds up within the electronic packages due to temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. The maximum Von Mises stress or principle stress criterion based on stress analysis and maximum energy release rate criterion based on fracture mechanics are two of the most popular criteria for failure prediction. However, it is well known that the stress calculation based on finite element analysis (FEA) is mesh dependent and stress fields around bonded corners showed singular behaviors. The objective of this work is to investigate a few interface delamination cases in IC packaging using stress analysis and fracture mechanics respectively. The approach is to quantify the stress, energy release rate and corresponding phase angle at room temperature and lead-free solder reflow temperature. A suitable criterion for the estimation of interface delamination will be proposed based on FEA and the results based on simulation will be compared with experiment study.