Xavier Baraton

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

Abstract For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

Abstract In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration ( C sat ) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.

Next generation eWLB (embedded wafer level BGA) packaging

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. There are some restrictions in possible applications for Fan-In WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. eWLB (embedded Wafer Level BGA) is a type of fan-out WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. Furthermore, 3D eWLB technology enables 3D IC and 3D SiP packaging with vertical interconnection. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. In this paper, there will be discussion of the recent advancements in 3D eWLB packaging and integration as well as what is being envisioned and developed to address future technology requirements in 3D packaging and 3D SIP. The advantage of 3D eWLB technology and applications of 3D packaging will be presented with several examples. The process flow of 3D eWLB fabrication, assembly and packaging challenges, and performance characteristics will be also discussed.

Effect of silver content and nickel dopant on mechanical properties of Sn-Ag-based solders

In this work, five solder materials of Sn-3.0Ag-0.5Cu (SAC305), Sn-2.0Ag-0.5Cu (SAC205), Sn-1.0Ag-0.5Cu (SAC105), Sn-1.0Ag-0.5Cu-0.05Ni (SAC105Ni0.05) and Sn-1.0Ag-0.5Cu-0.02Ni (SAC105M0.02) were tested using tensile loading at room temperature to investigate the Ag content and Ni dopant effect on solder mechanical properties, respectively. In addition, different testing temperature conditions including -35 deg.C, 25 deg.C, 75 deg.C and 125 deg.C were used for SAC105M0.02 solder to investigate the temperature effect on mechanical properties. Tensile test under different strain rates from 0.000011/s to 0.11/s was conducted to study the strain rate effect on material properties. Test results show that the material properties of modulus, UTS and yield stress increase with strain rate and Ag content, but decrease with temperature. The 500 ppm Ni dopant has the significant effect on material properties of Sn-Ag-based solder than 200 ppm Ni dopant. Lower modulus, yield stress and UTS, higher elongation can be achieved for SAC105M0.05 solder compared to SAC105M0.02 solder. The rate dependent and Ag content dependent material models were developed for Sn-Ag-Cu lead free solders. In addition, the temperature and rate dependent models were developed for SAC105M0.02 solder. The microstructures of different solder alloys were analyzed based on SEM images. It was found that Ag content affects the Ag3Sn intermetallic compound dispersion and Sn grain size. The microstructure of solder alloy has finely dispersed IMC and fine Sn grain size for the high Ag content solder, which make the solder exhibit high strength.

Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging

Integrated Circuits fabricated on silicon are assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demand for these electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in component level and board level reliability of next generation eWLB technologies including multi-RDL, thin eWLB, extra large eWLB with multi-chip. Standard JEDEC tests were carried out to investigate component level reliability and both failure analysis was performed to investigate potential structural defects. Daisychain eWLBs were assembled with different package size and different configuration as like thin or multi-RDL or multi-die. Test vehicles were also tested for drop and TCoB (Temperature on Board) reliability in industry standard test conditions. Next generation test vehicles passed both drop and TCoB tests. There was more than 50% improvement of characteristic lifetime with thinned eWLB in TCoB test because of its enhanced flexibility of package. This paper also presents study of package warpage behavior with temperature profile which is important for understanding of mechanical behavior of next generation 3D eWLBs.

Design analysis of solder joint reliability for stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveauxs approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder.

Challenges for extra large embedded wafer level ball grid array development

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Finite Element Analysis of Thermal Cycling Reliability of an Extra Large Thermally Enhanced Flip Chip BGA Package with Rotated Die

Since the introduction of Thermally Enhanced Flip Chip Ball Grid Array (TEFCBGA) packages, it has been one of the popular packaging options in the market for mid to high end devices in that it effectively improves both electrical and thermal performance of the product. However, to develop a robust TEFCBGA package with extra large body size of 55 mm × 55 mm is a no easy task, especially when it contains a Cu/Low-k die of 19 mm × 19 mm in size at the same time. The presence of such a large sized die not only brings about reliability issues, e.g. delamination at Inter-Layer Dielectric (ILD) interfaces, die cracking, early flip chip bump fatigue failure and excessive package warpage, but takes up most of the precious substrate real estate available, leaving little room for the neighboring passive components. To cope with this space constraint, the die is proposed to rotate by 45° with regard to the package outline, whereby a much more flexible layout of passive devices can be achieved. However, it has yet to answer whether this modified die arrangement creates more problems than it solves. This paper initially investigated the BGA and flip chip solder joint reliability of the baseline TEFCBGA package, i.e. with standard die layout, under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Global-local and multi-level sub-modeling techniques were employed for modeling of BGA solder balls and FC solder bumps respectively. Experiments were then carried out to assess the accuracy of the FEA model.

Characterization of silicon die strength with application to die crack analysis

After encapsulation, thermo-mechanical deformation builds up within the electronic packages due to temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. As the trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, they bring challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. One of the reliability problems, die crack, becomes more serious due to the larger die area compared with package size, thinner thickness and thermal mismatch between the respective materials within the package. Die strength can be adversely affected during various manufacturing processes, such as grinding and chipping. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work try to find the simple test method for determination of die strength to improve the scatter and try to differentiate the factors that affect the variability of die strength, in order to find out the causes of the weakness of the die strength. The surface conditions (roughness) of the specimens are determined by atomic force microscopy (AFM) and correlated to failure strength. A practical example is presented here that die cracking analysis has been done for a chip array thin core BGA (CTBGA) during thermal cycling. The die stress is calculated based on the finite element analysis (FEA) of CTBGA and the FEA-predicted die stress is used to predict the die failure rate compared with the experiment results.