Luc Garcia

A 5.4 mW/0.07 mm

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm2, or 0.23 mm2 when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.

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The aim of the 2.4GHz front-end receiver presented in this paper is the minimization of both cost and energy consumption, focusing on WPAN IEEE 802.15.4 transceivers. It includes the entire RF part, from the balun to the first stage of the channel filter, as well as the LO signal conditioning cells. The proposed architecture uses an unmatched inductorless LNA and a new clocking scheme on a standard passive mixer. Compared to previously reported IEEE 802.15.4 receivers, an area reduction by at least 70% is achieved. The power consumption is relatively low at 5.4mW with a state-of-the-art noise and linearity performance. The receiver front-end operates at 1.35V. It is implemented in a 90nm CMOS technology using two thick metals, and alucap with RFMOM capacitors.