Luc Vanwassenhove

Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways

Architectural studies have identified field-programmable gate arrays (FPGA) as a class of general-purpose very large scale integration components that could benefit from the introduction at the logic level of state-of-the-art massively parallel optical inter-chip interconnections. In this paper, we present a small-scale optoelectronic multi-FPGA demonstrator in which three optoelectronic enhanced FPGAs are interconnected by 2D Plastic Optical Fiber (POF) ribbon arrays. The full-custom FPGA chips consisting of an 8 X 8 array of very simple programmable logic cells are equipped with two optical sources and two receivers per FPGA cell yielding a maximum of 256 optical links per chip. The optical links are designed for signaling rates of 80 to 100 Mbit/s (160 to 200 Mbaud using Manchester coded data) compatible with the maximum clock frequency of the, in 0.6 micrometers CMOS implemented, FPGA chips. The results of parallel link experiments between such modules with both VCSELs and LEDs as sources will be shown. A large scale parallel bit error rate experiment at 90 Mbit/s/channel between two half-populated VCSEL-based FPGA modules with 112 of their 128 channels operational at bit error rates below 10-13 on all active channels (approximately equals 10 Gbit/s/chip) proves the feasibility of this approach. We first briefly discuss the general architecture and the realization of the optoelectronic FPGA demonstrator system. We then present measurement results on the available modules, followed by some conclusions on this work.

Two-dimensional optical interconnect between CMOS IC's

The central issue of optically interconnected integrated circuits (OIIC) concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers throughput data interconnects on inter-chip and MCM level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator, implementing state-of-the-art technology, and two link demonstrators, aiming at a high speed approach with 16 channels (Gigalink), and a low power, high density approach on 100 pm pitch with 100 channels (Photonlink). In the paper, progress and results in the project on architecture, components, optical pathways and mounting techniques for the system demonstrator will be highlighted. This system demonstrator aims at using a smart-pixel like interconnect structure to create a logically 3-D architecture, conceptually consisting of a number of electronic planes (electrical FPGAs), that are interconnected bidirectionally along a regular pattern that runs across the chip surface. The full-custom CMOS FPGA circuit is an 8/spl times/8 array of simple configurable logic blocks (a 4-bit function table, one flip-flop), interconnected by a programmable 6-6 switch matrix fabric, including the access to off-chip optical interconnections. The optical components consist of two 8/spl times/8 source arrays (either LEDs or VCSELs) and two 8/spl times/8 InP detector arrays, which are flip-chip bonded to the CMOS circuit and actually overlay part of the CMOS circuits. Electronic driving and receiving circuits are realised in CMOS, and are intermixed with the digital circuits. Each of the 256 optical channels is designed to operate at an information rate of 80 Mbit/s. To ensure reliable communication over so many parallel channels in a noisy digital environment, AC-coupled communication with Manchester coded data is used in the design. The optical pathways between the central chip and its two neighbours consists of removable 8/spl times/16 POF ribbons. Preliminary tests of the CMOS functionality have been completed with good results. A methodology for hybrid assembly, packaging and passive alignment of all components has been implemented. The hybridisation and packaging steps of the CMOS chips and the optical components, final assembly and measurements are discussed.

Demonstration of 2-D plastic optical fibre based optical interconnect between CMOS ICs

The design and fabrication of a digital system demonstrator implementing 2D optical interconnect via a POF ribbon are discussed. This demonstrator implements 256 optical I/O channels per chip. Each chip, a custom FPGA CMOS design, implements digital and analogue functionality.

2D inter-chip optical interconnect

Abstract The main reason for the expected I/O-bottleneck in future data processing systems, is the increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion, EMI) result in an increasing mismatch between silicon processing capabilities and interconnect performance, pushing packaging costs and required effort to significantly higher levels. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European community funded ESPRIT project OIIC (“Optically Interconnected Integrated Circuits”). The central issue of OIIC concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers high-throughput data interconnects on inter-chip and multi-chip module (MCM) level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator with an 8×8 FPGA digital core, implementing state-of-the-art technology, and two link demonstrators, aiming at a high-speed approach with 16 channels (Gigalink), and a low power, high-density approach on 100 μm pitch with 100 channels (Photonlink). For the demonstrators, flexible guided wave optical pathways are used. In this paper, progress and results in the project on architecture, components, optical pathways and mounting techniques are highlighted, with main focus on the system demonstrator.

A room temperature flip-chip mounting technique for laser diodes on silicon motherboards

In this presentation, a relatively simple mounting method is suggested for flip-chip mounting of arrays of edge-emitting laser diodes to arrays of fibers. What really makes the difference with known methods is the use of a room temperature mounting process using a transparent UV-curing, non conducting glue for the fixation of arrays of laser diodes. Apart from power budget problems, the only problem to be solved was the influence of the glue on the laser facets. This has been solved by the application of coatings.

Optical area I/O enhanced FPGA with 256 optical channels per chip

It is our goal to demonstrate the viability of massively parallel optical interconnections between electronic VLSI chips. This is done through the development of the technology necessary for the realization of such interconnections, and the definition of a systems architecture in which these interconnections play a meaningful role. Field-programmable gate arrays (FPGA) have been identified as a class of general-purpose very large scale integration components that could benefit from the massive introduction of state-of-the-art optical inter-chip interconnections at the logic level. In this paper, we present the realization of a small-scale optoelectronic FPGA with 8 X 8 logic cells, containing two optical sources and two receivers per FPGA cell yielding a total of 256 links per chip. These FPGA chips designed to operate with information rates of 80 Mbit/s/link will be used in a three- chip demonstrator system as a test bed for the concepts above. We first identify the reason why we think optical interconnects can provide added value in FPGAs. The next sections briefly discuss the general architecture of our demonstrator system and the realization of the optoelectronic FPGA. We then present first measurement results followed by ongoing work and conclusions.

An active electro-optical loop and dipole probe for electromagnetic near-field measurements

An active electro-optical dipole and loop probe have been developed to measure electromagnetic near-fields. For the assembly of the probes attention has been paid to the sensitivity of the probe, to the susceptibility of the probes to interfering electromagnetic fields and to their high-frequency behaviour. The electro-optical loop probe (1 cm/spl times/1 cm) has a sensitivity comparable to that of conventional loop probes of the same size, can measure magnetic fields up to 0.1 mA/m and has a linear dynamic behaviour of at least 60 dB. The electro-optical dipole probe (h/sub eff/=1 cm) has a sensitivity that is better than that of conventional dipole probes of comparable size, can measure electric fields up to 30 mV/m and has a linear dynamic behaviour of at least 60 dB. In contradiction to most of the reported near-field probes with an optical link there is no conversion of the antenna signal to a DC-signal which means that all the spectral information of the electromagnetic field is preserved. This makes these probes excellent instruments for diagnostic EMC-measurements.

Microgroove fabrication with excimer laser ablation techniques for optical fiber array alignment purposes

Currently, an ever increasing need for bandwidth, compactness and efficiency characterizes the world of interconnect and data communication. This tendency has already led to serial links being gradually replaced by parallel optical interconnect solutions. However, as the maximum capacity for the latter will be reached in the near future, new approaches are required to meet demand. One possible option is to switch to 2D parallel implementations of fiber arrays. In this paper we present the fabrication of a 2D connector for coupling a 4x8 array of plastic optical fibers to RCLED or VCSEL arrays. The connector consists primarily of dedicated PMMA plates in which arrays of 8 precisely dimensioned grooves at a pitch of 250 micrometers are introduced. The trenches are each 127 micrometers deep and their width is optimized to allow fixation of plastic optical fibers. We used excimer laser ablation for prototype fabrication of these alignment microstructures. In a later stage, the plates can be replicated using standard molding techniques. The laser ablation technique is extremely well suited for rapid prototyping and proves to be a versatile process yielding high accuracy dimensioning and repeatability of features in a wide diversity of materials. The dependency of the performance in terms of quality of the trenches (bottom roughness) and wall angle on various parameters (wavelength, energy density, pulse frequency and substrate material) is discussed. The fabricated polymer sheets with grooves are used to hold optical fibers by means of a UV-curable adhesive. In a final phase, the plates are stacked and glued in order to realize the 2D-connector of plastic optical fibers for short distance optical interconnects.

Realisation of highly efficient and high-speed Resonant Cavity LED for coupling to Plastic Optical Fibres

Planar Resonant Cavity LEDs (RCLEDs) are suitable light sources for parallel interchip interconnect links, due to their high efficiency, zero-threshold, low voltage, high reliability and high speed characteristics. The through- substrate emitting RCLEDs, optimized for Polymer Optical Fiber (POF) coupling, consist of an InGaAs quantum sandwiched between a metal mirror and a distributed Bragg reflector. The RCLEDs are arranged in 8 X 8 arrays with 250 um pitch. The arrays have been mounted onto glass carriers, and the coupling efficiency into POF, the far- field pattern and the modulation characteristics are measured. The overall quantum efficiency of the devices with 50 um diameter was found to be 13.4%, the QE into POF was 3.7%. The large-signal transient behavior of the devices has been investigated. Using a high-speed pulse source, nanosecond rise and fall times have been measured. Wide open eye diagrams at 1 Gbit/s were obtained using voltage pulse drivers. These data were compared to theoretical results based on a non-linear rate equations model.

Low‐cost fibre‐chip coupling for electro‐optic EMC‐probes

A straightforward flip‐chip mounting technique is described using gold bumps, a silicon motherboard and non‐conductive adhesives to fabricate electro‐optical modules coupling light from arrays of laser diodes into arrays of fibres. This enables the fabrication of non‐hermetic, potentially cheap modules for short‐distance, parallel‐optical interconnection. As an application, the realisation of a compact, active electro‐optical dipole and loop probe is presented. During assembly of the probes, attention was paid to sensitivity, susceptibility to interfering electromagnetic fields and to high‐frequency behaviour. The probes show sensitivities comparable with, or better than, conventional probes of the same size. They show a linear dynamic behaviour of at least 60dB, and measure electric fields up to 30mV/m or magnetic fields up to 0.1mA/m, respectively. The antenna signal modulates the optical signal of a biased laser diode, and because all the spectral information of the electromagnetic field is preserved during measurement, these probes are excellent instruments for diagnostic EMC‐measurements with a high spatial resolution.