Luca Di Nunzio

Spiking neural networks based on LIF with latency: Simulation and synchronization effects

In this paper, a work on spiking neural networks based on a model of a kind of Leaky Integrate-and-Fire (LIF) neuron with latency is presented. Efficient simulations are carried out through an ad hoc event-driven approach, highlighting some particular effects of synchrony in a simple feedforward network topology. These results are consistent with literature results and, thanks to the implementation of the biologically plausible latency effect in the model, new results have emerged from the simulations. The authors plan to apply these results in the near future to applications in which this kind of neural networks and Digital Signal Processing (DSP) applications can be merged to obtain powerful nonlinear DSP techniques. In the plan of the authors is also the definition of a hardware prototype of the network based on analog/digital techniques.

Fine-grain Reconfigurable Functional Unit for embedded processors

In standard word-oriented microprocessors, the processing of short data decreases the computation performance. In order to overcome this issue various methods based on reconfigurable architectures have been presented in the literature [1] [2] [3]. These structures are normally composed by an array of elementary reconfigurable cells. A common solution for elementary reconfigurable cells realization is based on Look-Up Tables (LUTs). In [4] [5] the authors proposed a new Reconfigurable Functional Unit (RFU) based on full adders and reprogrammable interconnects named ADAPTO. The final aim is to obtain a new structure that requires less silicon area and power, being ever faster than the “traditional” solutions. In this paper we present the main characteristics of the proposed structure evaluating its performance (in terms of speed-up and complexity) when integrated in an embedded processor.

Arithmetic/logic blocks for fine-grained reconfigurable units

Processing performance of algorithms implemented on conventional processors or DSP can degrade when bit level operations are involved. This degradation is related to the characteristics of logic and arithmetic operators present inside the processors, that are optimized for word level operations. Different methods have been proposed for overcoming this problem. A very interesting method is based on the introduction of specific logic and arithmetic units, jointly to the conventional integer or floating-point units. Due to the great variability of the bit level operations that must be performed, a fixed structure unit is not very suitable for this application. This fact has suggested the introduction of units based on arrays of reconfigurable cells, as the RAM based Look-up Tables. In this paper an alternative reconfigurable cell, specialized for the realization of bit manipulating unit, is described and evaluated. The comparison results show that the proposed solution is very efficient in terms of number of transistors (or silicon area) if compared to a conventional approach based on Look-up Table.

Hardware design of LIF with Latency neuron model with memristive STDP synapses

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks

A ZnO-rGO composite thin film discrete memristor

Ultrathin 2D materials such as TiO2, WOx, NiO, ZnO, VO2 and graphene, offer scope for low power, highly dense and ultra-fast electronic devices. Due to their extraordinary physical and electrical/electronic property. In this work, a novel forming free memristor has been realized based on hybrid film of ZnO-rGO. The structure of the device is Metal-Insulator-Metal structure, where the Zinc Oxide- Reduced Graphene Oxide (ZnO-rGO) thin film is sandwiched between Silver (Ag) and Fluorine-doped tin oxide (FTO) coated glass. Free oxygen vacancies were created within the composite film by using high temperature annealing at 500 degrees Celsius. We demonstrate bipolar resistive switching behavior of the new device. Also we show that the variation of the conductance of the device is related to delay time of the applied input voltage sweep.

An a VLSI driving circuit for memristor-based STDP

The main goal in realizing a VLSI (analog VLSI) systems able to mimic functionalities of biological neural networks is pointed to the reproduction of realistic synapses. Indeed, because of the relative high synapse/neuron ratio, especially in the case of extremely dense networks (i.e., reproduction of a real scenario), synapses represent a considerable limitation in terms of waste of silicon area and power consumption as well. Thanks to advancement made in the implementation of memristor, the interest in bio-inspired neural network design has been renewed. Memristors have tunable resistance which depends on its past state; this is analogous to the operating mode of biological synapses. In this paper, we present the circuit implementation of a simple memristor-based neural network. Here, we propose a driving circuit model that not requires specific shape input pulses to change the memristor conductance (i.e., synaptic strength), but it can be driven by arbitrary shaped input pulses. Moreover, this prototype circuit offers the chance of emulating the standard STDP behavior allowing “controlled” changes for the synaptic weights. Some preliminary experimental results are reported to validate the proposed driving circuit.

A Wireless Sensor Node Based on Microbial Fuel Cell

In recent years there has been a widespread use of wireless sensor networks that found their application in complex systems where a lot of physical quantities have to be monitored. This nodes must deal with different physical quantities and must operate in different environments. In many applications the most critical aspect is the power supply, because frequently is possible to provide power supply by wires and sometimes the use of batteries is not an acceptable solution. This latter limitation occurs when the number of nodes is very high and/or the operation of battery substitution is very complex. Moreover, environmental requests for pollutant reduction and for renewable materials represents another limitation for the use power supply generation based on battery. For these reasons it can be useful to develop power sensor nodes which use energy harvested directly on the operation site, making the sensors energetically autonomous. In this paper we present an innovative sensor node based on Microbial Fuel Cells (MFCs). The implemented node proves the viability of MFC for the energy harvesting in sensor networks. This system uses the electric energy provided by the bacteria present in the soil as power supply for an ultra low power electronic system, based on a micro-controller equipped with a digital transceiver. The designed system is able to acquire data from a sensor and transmit them wirelessly. The scarcity of available energy and the limited voltages of the MFC require to design new schemes for the energy harvesting and the power supply, as well as new working modes which must satisfy the strong energy constraints.

A Reconfigurable Functional Unit for Modular Operations

The efficiency of standard microprocessors decreases when operations on short data are performed because they are optimized to perform operations on fixed size data. Short data processing and bit manipulation can be accelerated integrating a Reconfigurable Functional Unit (RFU ) in parallel with the ALU. An RFU is a tightly coupled integrated Reconfigurable Array used to speed-up the computation of a set of operations for which standard microprocessors are not optimized. In this paper we show the benefit of using the Adder-based Dynamic Architecture for Processing Tailored Operators (ADAPTO RFU) [1, 2, 3] (a full adder based RFU) on modular operations. In particular we describe how to speed up the modular addition and the Montgomery Multiplication by using the ADAPTO RFU.

A Wireless Sensor Node for Acoustic Emission Non-destructive Testing.

In this paper a wireless sensor node for Acoustic Emission (AE) analysis has been proposed. This node can be used to simplify the in-force procedures for the structural integrity verification of pressure tanks. This procedure is currently based on periodic checks and consequently does not allow a real-time monitoring. The proposed wireless sensor node is compatible with commonly used AE sensors available on market and can be integrated in a wireless sensor network for real time monitoring increasing the security of the plant.

FPGA Implementation of a Low-Power QRS Extractor

Among the bio-signals, the ECG is the most important waveform used for health analysis. It provides information about the heart rate, rhythm, and morphology of heart. Today, thanks to the development of advanced wearable devices, it is possible to track patient conditions outside hospital setting for several days. In such a context, the low power consumption becomes one of the crucial challenges in the development of wearable systems. In this paper, a low power implementation of Pan and Tompkins algorithm for QRS extraction is proposed. Results show that an appropriate hardware implementation significantly reduces the DSP portion power consumption of the algorithm compared with other implementation proposed in literature.