Rocco Fazzolari

Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit

Advanced bit manipulation operations are not efficiently supported by standard microprocessors since they are optimized for fixed data size operations. In literature several hardware solutions are proposed to overcome this problem [1], [3] and [4]. In this work we present the experimental results of a new architecture based on LEON-2 and a simplified version of ADAPTO [1] (Adder-based Dynamic Architecture for Processing Tailored Operators), acting as a co-processor. For our experiments we run a set of Bit Manipulation Algorithms on the LEON-2 processor in presence and absence of the ADAPTO unit. This permits to measure the speed-up factor obtained using the proposed reconfigurable co-processor.

Butterfly and Inverse Butterfly nets integration on Altera NIOS-II embedded processor

The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described in [1], [2] and the Altera NIOS-II processor [5]. The BMU, described in VHDL, has been integrated in the processor using the Custom Logic feature [6] and implemented on an Altera-Stratix FPGA.

Implementation of the AES algorithm using a Reconfigurable Functional Unit

Nowadays programmable devices (microprocessors and DSPs) are based on complex architectures optimized for obtaining maximum speed performances that degrades when the implemented application is mostly based on operations on single bit or subset of bits. This kind of data processing and bit manipulation operations can be accelerated by using a Reconfigurable Functional Unit (RFU). In this paper the benefits of using the ADAPTO RFU (Adder-Based Dynamic Architecture for Processing Tailored Operators) [1] [2] to speed up the Advanced Encryption Standard algorithm (AES) is investigated. The paper shows how the ADAPTO architecture is useful for the acceleration the AES algorithm due the efficient implementation of the most complex operations of the algorithm. A comparison in terms of number of assembly instructions is given.

TDES cryptography algorithm acceleration using a reconfigurable functional unit

Many cryptography algorithm contain a lots of data bit manipulation operations. Unfortunately, the Instruction Set Architecure (ISA) of general purpose microprocessors is usually word oriented. Consequently the execution of this kind of algorithms is not optimized and the computation of data represented by single bits or sub-words can require several clock cycles. Reconfigurable hardware accelerators oriented to the bit manipulation could accelerate the computation of these algorithms increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the speed-up factor obtained for the implementation of TDES (Triple Data Encryption Standard) algorithm when a Reconfigurable Functional Unit ADAPTO [1] is integrated with a RISC microprocessor (the Altera NIOS-II soft processor [2]). The ADAPTO unit, described in VHDL (VHSIC Hardware Description Language), has been implemented on an Altera-Stratix II FPGA and integrated with the Nios soft processor using the Custom Logic feature [4]. The objective is the measurement of the speed-up factor related to the introduction of the reconfigurable hardware accelerator.

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving

Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessors architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors.

Fine-grain Reconfigurable Functional Unit for embedded processors

In standard word-oriented microprocessors, the processing of short data decreases the computation performance. In order to overcome this issue various methods based on reconfigurable architectures have been presented in the literature [1] [2] [3]. These structures are normally composed by an array of elementary reconfigurable cells. A common solution for elementary reconfigurable cells realization is based on Look-Up Tables (LUTs). In [4] [5] the authors proposed a new Reconfigurable Functional Unit (RFU) based on full adders and reprogrammable interconnects named ADAPTO. The final aim is to obtain a new structure that requires less silicon area and power, being ever faster than the “traditional” solutions. In this paper we present the main characteristics of the proposed structure evaluating its performance (in terms of speed-up and complexity) when integrated in an embedded processor.

Hardware design of LIF with Latency neuron model with memristive STDP synapses

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural networks

FPGA implementation of a low-area/high-SFDR DDFS architecture

This paper describes the FPGA implementation of a low area and high Spurious Free Dynamic Range (SFDR) Direct Digital Frequency Synthesizer (DDFS). The proposed architecture derives from the one proposed in [1] and fits perfectly in modern FPGA having DSP Blocks and/or embedded multipliers. The DDFS model in [1] was modified in order to reduce further the ROM size by a factor of 2 without worsen the SFDR and was implemented on a XILINX Virtex 5 FPGA. In this work we show that using the proposed hardware architecture, it is possible to reach very high SFDR (more than 157 dB) without impacting on the area occupancy. In fact traditional LUT-based DDFS has an exponential relationship between the ROM size and the number of phase bits.

A ZnO-rGO composite thin film discrete memristor

Ultrathin 2D materials such as TiO2, WOx, NiO, ZnO, VO2 and graphene, offer scope for low power, highly dense and ultra-fast electronic devices. Due to their extraordinary physical and electrical/electronic property. In this work, a novel forming free memristor has been realized based on hybrid film of ZnO-rGO. The structure of the device is Metal-Insulator-Metal structure, where the Zinc Oxide- Reduced Graphene Oxide (ZnO-rGO) thin film is sandwiched between Silver (Ag) and Fluorine-doped tin oxide (FTO) coated glass. Free oxygen vacancies were created within the composite film by using high temperature annealing at 500 degrees Celsius. We demonstrate bipolar resistive switching behavior of the new device. Also we show that the variation of the conductance of the device is related to delay time of the applied input voltage sweep.

Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach.

Today, a number of applications need to process large bandwidth signals. These applications frequently require the use of fast ADCs and very efficient DSP structures that are difficult to design. An interesting solution for facing these issues is the Compressive Sensing (CS) method, which, assuming to know some properties of the signal, allows to reduce the sampling rate well below the Nyquist rate. A negative aspect of CS is the need to introduce an additional element for the reconstruction the sampled signal. This reconstruction requires techniques that generally have an high computational cost, representing a critical element for a real-time implementation of CS systems. In this work we present the implementation of one of these reconstruction algorithms, named Orthogonal Matching Pursuit (OMP). This algorithm involves heavy computational cost (in particular for the matrix computation), which limits its use in the case of a strictly real-time applications, as in the case of radar systems. To overcome this limitation authors propose a solution that uses for the implementation a mixed software/hardware approach. The proposed architecture was implemented on the Xilinx ZYNQ FPGA. The experimental results show a significant speed-up of the algorithm.