Roberto Saletti

Ultralow-power adiabatic circuit semi-custom design

This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.

Batteries and battery management systems for electric vehicles

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

Design and Verification of Hardware Building Blocks for High-Speed and Fault-Tolerant In-Vehicle Networks

This paper presents the design, implementation, and validation of a FlexRay transceiver and a SpaceWire (SpW) router and interface, which constitute the main hardware building blocks of the two in-vehicle communication standards. The FlexRay protocol features data rates up to 10 Mb/s and time- and event-triggered transmissions, along with scalable fault-tolerance support, and it is expected to become the standard network for X-by-wire and active safety automotive systems. However, collision avoidance and driver-assistance applications based on camera/radar sensors require data rates up to hundreds of megabits per second as well as fault tolerance, features that can hardly be covered by current or expected automotive standards. In this scenario, a promising technology seems to be the new SpW protocol, currently used in avionics and aerospace.

Ultra low-noise preamplifier for low-frequency noise measurements in electron devices

The design and realization of an ultra-low-noise, high-input-impedance amplifier for low-frequency noise measurements in electronic devices is presented. Special care is devoted to the solution of typical problems encountered in the design of low-noise low-frequency equipment, such as power supply noise and temperature fluctuations. The ultra-low-noise preamplifier has a bandwidth of over seven decades with a low-frequency roll-off of 4 mHz. The noise characteristics obtained are sensibly better than those of commercial preamplifiers commonly adopted in low-frequency noise measurements. The application of this preamplifier to the realization of standard 1/f/sup gamma / noise generators is presented. >

High-Efficiency Digitally Controlled Charge Equalizer for Series-Connected Cells Based on Switching Converter and Super-Capacitor

The charge stored in series-connected lithium batteries needs to be well equalized between the elements of the series. We present here an innovative lithium-battery cell-to-cell active equalizer capable of moving charge between series-connected cells using a super-capacitor as an energy tank. The system temporarily stores the charge drawn from a cell in the super-capacitor, then the charge is moved into another cell without wasting energy as it happens in passive equalization. The architecture of the system which employs a digitally-controlled switching converter is compared with the state of the art, then fully investigated, together with the methodology used in its design. The performance of the system is described by presenting and discussing the experimental results of laboratory tests. The most innovative and attractive aspect of the proposed system is its very high efficiency, which is over 90%.

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.

A Novel Bit-Level Systolic Array Median Filter

This paper presents examples of the application of ethopharmacology to the study of aggression. Low doses of benzodiazepines may increase aggression under appropriate conditions. In various animal models in male and female rats and mice the aggression enhancing effects are particularly marked when aggression is inhibited by internal or external events. It is therefore suggested that benzodiazepines have no direct effect on aggression, but modulate inhibitory factors which regulate aggression.

A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-/spl mu/m CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.

Parametrized and reusable VLSI macro cells for the low-power realization of 2-D discrete-cosine-transform

The problem of an efficient VLSI realization of the 2-D discrete-cosine-transform and its inverse is addressed in this paper. Two circuits implementing both functions are discussed and characterized from the high-level architectural choices down to the gate-level synthesis on different standard-cell target technologies. The circuits are designed as parametric intellectual property (IP) cells according to a design reuse policy that allows the user to select the most convenient solution for the considered application. Synthesis results show that the circuits are suitable for real time processing of various image formats adopted in H.263/MPEG compression standards. Power consumption reduction methods (clock gating, switching activity reduction) are used according to the statistics of the input signals to reduce the dissipated power. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Finally, a comparison with dedicated full-custom low-power circuits presented in the literature show that these IP cells stand for flexibility, parametrization and reusability, still maintaining comparable power consumption and area occupation.

A 1/f/sup gamma / power spectrum noise sequence generator

The authors discuss the design of a noise sequence generator that provides a stationary process that follows a 1/f/sup gamma / law over a limited frequency band. The kind of noise is generated by passing a white-noise sequence in a digital filter characterized by a frequency-response-squared module proportional to 1/f/sup gamma /. The design of the digital filter is performed in a straightforward manner by applying the matched z-transform to the transfer function of a proper analog filter. The digitalization error is also discussed, and a simple and useful design method for a flicker-like noise generator with exponents gamma between -2 and 2 is reported. It is shown that the Barnes-Jarvis 1/f noise generator can easily be derived as a particular case with gamma =1. >