Luca Pezzoni

Frame concealment for H.264/AVC decoders

The H.264/AVC offers a high video coding efficiency and is the first standard that provides an explicit support for the transmission of multimedia content over a packed switched network, specifying a network abstraction layer (NAL). If we consider the transmission of a low resolution video sequence over a wireless LAN network or a UMTS link, we can usually observe that a coded picture typically fits the packet size, therefore a transmission error produces the loss of a whole frame. In this paper, we propose a novel technique to perform the concealment of a whole frame for H.264/A VC video decoders.

An innovative, high quality and search window independent motion estimation algorithm and architecture for MPEG-2 encoding

This paper describes an innovative, pipelined, cache-based architecture for a motion estimation coprocessor. The coprocessor is based on a predictive/recursive algorithm whose computational complexity is low and not dependent on the search window. The synergies between the architecture and algorithms features allow a high picture quality, low-area, low-bandwidth, unlimited search window implementation.

Adaptive gop size control in h.264/avc encoding based on scene change detection

An efficient method is proposed to dynamically adapt the group of pictures (GOP) size in H.264/AVC encoding, by on-the-fly identification of scene changes in the input video signal. Intra coding picture decision is taken at the end of the pre-analysis phase of a fast motion estimation method based on spatial-temporal motion correlation. With negligible additional computation and memory requirements, the proposed method allows improving the compression of the whole coding process by up to 15%, without affecting the overall image quality

Detailed rate-distortion analysis of H.264 video coding standard and comparison to MPEG2/4

H.264 is an emerging video coding standard, providing significant improvements with respect to its ancestors, like MPEG-2 and MPEG-4. In this paper, we present an evaluation of the most important H.264 coding tools in terms of visual quality and compression efficiency

Slice header reconstruction for H.264/AVC robust decoders

For H.264/AVC encoded video sequences, a transmission error in the bit-stream can affect either the underlying codeword or even the subsequent symbols, thus resulting in a great degradation of the received images. In this paper we present a powerful algorithm of slice-header reconstruction for H.264/AVC decoders: after having decoded the corrupted header of a slice, it can recover most of the related slice data without requiring any interaction from the encoder side. Our method exploits the redundancy available when slice partitioning is applied, that is, the repetition of the most important header parameters in every slice of a picture. The proposed approach allows to recover high quality pictures from the corresponding corrupted slices for a wide range of bit error rates (BER)

An optimized software implementation of the HEVC/H.265 video decoder

In this paper an optimized implementation of the HEVC video decoder is shown. The solutions developed to support the new features of HEVC are shown together with the achieved performance. The HEVC decoder complexity has been evaluated and the most demanding modules have been optimized exploiting SIMD instructions. Even though the here described concepts have a general value, the effectiveness of the proposed solutions has been verified on the ARM architecture. The selected architecture is ARM Cortex A9 with NEON SIMD extension. We will demonstrate that the resulting real-time HEVC software decoder can decode 720p (1280x720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.

An Efficient SIMD Implementation of the H.265 Decoder for Mobile Architecture

This paper focuses on an efficient optimization of the H.265 video decoder on suitable architectures for mobile devices. The solutions developed to support the H.265 features, and the achieved performances are shown. The most demanding modules have been optimized with Single Instruction Multiple Data (SIMD) instructions and we keep in special account the memory handling, with the minimization of the memory transfer. The effectiveness of the proposed solutions has been demonstrated on ARM architecture. In particular, we have selected the dual-core Cortex A9 processor with NEON SIMD extension.

Low-complexity motion estimation for the scalable video coding extension of H.264/AVC

The recently standardized Scalable Video Coding(SVC) extension of H.264/AVC allows bitstream scalability with improved rate-distortion efficiency with respect to the classical Simulcasting approach, at the cost of an increased computational complexity of the encoding process. So one critical issue related to practical deployment of SVC is the complexity reduction, fundamental to use it in consumer applications. In this paper, we present a fully scalable fast motion estimation algorithm that enables an excellent complexity performance.

H.264 video decoding compatible with Vector Graphics

This work introduces a novel way to decode a video H.264 stream. An advanced Vector Graphics pipeline has been modified and used to decode H.264 Main Profile video bit streams, instead of using a native decoder. The Vector Graphics GPU can be used to perform tasks for which it was not originally intended: acceleration of video at resolutions between QCIF to Full HD without loss or any drift of quality compared to the H.264 native decoder output.