Paolo Lambruschini

An efficient multi-core SIMD implementation for H.264/AVC encoder

The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

Real-time transmission and storage of video, audio, and health data in emergency and home care situations

The increase in the availability of bandwidth for wireless links, network integration, and the computational power on fixed and mobile platforms at affordable costs allows nowadays for the handling of audio and video data, their quality making them suitable for medical application. These information streams can support both continuous monitoring and emergency situations. According to this scenario, the authors have developed and implemented the mobile communication system which is described in this paper. The system is based on ITU-T H.323 multimedia terminal recommendation, suitable for real-time data/video/audio and telemedical applications. The audio and video codecs, respectively, H.264 and G723.1, were implemented and optimized in order to obtain high performance on the system target processors. Offline media streaming storage and retrieval functionalities were supported by integrating a relational database in the hospital central system. The system is based on low-cost consumer technologies such as general packet radio service (GPRS) and wireless local area network (WLAN or WiFi) for lowband data/video transmission. Implementation and testing were carried out for medical emergency and telemedicine application. In this paper, the emergency case study is described.

An optimized software implementation of the HEVC/H.265 video decoder

In this paper an optimized implementation of the HEVC video decoder is shown. The solutions developed to support the new features of HEVC are shown together with the achieved performance. The HEVC decoder complexity has been evaluated and the most demanding modules have been optimized exploiting SIMD instructions. Even though the here described concepts have a general value, the effectiveness of the proposed solutions has been verified on the ARM architecture. The selected architecture is ARM Cortex A9 with NEON SIMD extension. We will demonstrate that the resulting real-time HEVC software decoder can decode 720p (1280x720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.

Supervision analysis and control system of photovoltaic power plants

This paper describes a supervision system able to handling the data collection from photovoltaic implants, their analysis allowing providing prevision and control of energy production. The supervision system integrates different functionality usually demanded to single subsystems and advanced features devoted to the implants maintenance and security. The supervision system is able to interact with the PV plant varying its functionality.

Control of AC-DC matrix converter using digital PLL

In this paper, the implementation of a DSP controlled ac-dc matrix converter is presented. A Phase Locked Loop is used to synchronize the high frequency ac voltage synthesized by the matrix converter with the three phase input line. This solution allows obtaining a stable output dc voltage even in case of non ideal input phases, which is the typical actual input in an industrial environment. Experimental results, obtained with a 5kW prototype and compared with computer simulated model results, are shown. Functional issues are discussed and design solutions proposed and implemented.

Single phase inverter grid connected, controlled by fundamental harmonic calculation

In this paper a single phase inverter grid connected implementation is presented. The proposed solution is based on the calculation of the input line fundamental harmonic using a DSP processor. Our aim is to increase the inverter performance through a better synchronization with the grid and achieving a unitary power factor even in case of distorted input line, usually present in industrial environments. Typical application is, but not limited to, the exploitation of solar or wind energy. The system implementation most critical issues and results achieved with a 1.5kW prototype are shown.

An Efficient SIMD Implementation of the H.265 Decoder for Mobile Architecture

This paper focuses on an efficient optimization of the H.265 video decoder on suitable architectures for mobile devices. The solutions developed to support the H.265 features, and the achieved performances are shown. The most demanding modules have been optimized with Single Instruction Multiple Data (SIMD) instructions and we keep in special account the memory handling, with the minimization of the memory transfer. The effectiveness of the proposed solutions has been demonstrated on ARM architecture. In particular, we have selected the dual-core Cortex A9 processor with NEON SIMD extension.

Optimized packet pre-filtering for analysis of IP traffic on high-speed networks

In this paper an efficient FPGA implementation of a packet pre-filtering algorithm based on Bloom filter is presented. In high speed link the traffic classification involves a very large amount of data per each packet processed (header and payload analysis). This leads to use hardware with high computational power and very expensive, in order to support requirement of real-time classification. Our system, reducing the data flow sent to the classifier allows a real-time classification with reduced hardware resources.

A DSP controlled three phase AC-DC matrix converter

In this paper, the implementation of a DSP controlled AC-DC matrix converter is presented. Experimental results, obtained with a 5 kW prototype and compared with analogous results of a computer simulated model, are shown. Functional issues are discussed and design solutions proposed and implemented.