Lucas Francisco Wanner

Variability-aware duty cycle scheduling in long running embedded sensing systems

Instance and temperature-dependent leakage power variability is already a significant issue in contemporary embedded processors, and one which is expected to increase in importance with scaling of semiconductor technology. We measure and characterize this leakage power variability in current microprocessors, and show that variability aware duty cycle scheduling produces 7.1× improvement in sensing quality for a desired lifetime. In contrast, pessimistic estimations of power consumption leave 61% of the energy untapped, and datasheet power specifications fail to meet required lifetimes by 14%. Finally, we introduce a duty cycle abstraction for TinyOS that allows applications to explicitly specify lifetime and minimum duty cycle requirements for individual tasks, and dynamically adjusts duty cycle rates so that overall quality of service is maximized in the presence of power variability.

Hardware Variability-Aware Duty Cycling for Embedded Sensors

Instance and temperature-dependent power variation has a direct impact on quality of sensing for battery-powered long-running sensing applications. We measure and characterize the active and leakage power for an ARM Cortex M3 processor and show that, across a temperature range of 20 -60, there is a 10% variation in active power, and a variation in leakage power. We introduce variability-aware duty cycling methods and a duty cycle (DC) abstraction for TinyOS which allows applications to explicitly specify the lifetime and minimum DC requirements for individual tasks, and dynamically adjusts the DC rates so that the overall quality of service is maximized in the presence of power variability. We show that variability-aware duty cycling yields a improvement in total active time over schedules based on worst case estimations of power, with an average improvement of across a wide variety of deployment scenarios based on the collected temperature traces. Conversely, datasheet power specifications fail to meet required lifetimes by 7%-15%, with an average 37 days short of the required lifetime of 1 year. Finally, we show that a target localization application using variability-aware DC yields a 50% improvement in quality of results over one based on worst case estimations of power consumption.

VarEMU: an emulation testbed for variability-aware software

Modern integrated circuits, fabricated in nanometer technologies, suffer from significant power/performance variation across-chip, chip-to-chip and over time due to aging and ambient fluctuations. Furthermore, several existing and emerging reliability loss mechanisms have caused increased transient, intermittent and permanent failure rates. While this variability has been typically addressed by process, device and circuit designers, there has been a recent push towards sensing and adapting to variability in the various layers of software. Current hardware platforms, however, typically lack variability sensing capabilities. Even if sensing capabilities were available, evaluating variability-aware software techniques across a significant number of hardware samples would prove exceedingly costly and time consuming. We introduce VarEMU, an extension to the QEMU virtual machine monitor that serves as a framework for the evaluation of variability-aware software techniques. VarEMU provides users with the means to emulate variations in power consumption and in fault characteristics and to sense and adapt to these variations in software. Through the use (and dynamic change) of parameters in a power model, users can create virtual machines that feature both static and dynamic variations in power consumption. Faults may be injected before or after, or completely replace the execution of any instruction. Power consumption and susceptibility to faults are also subject to dynamic change according to an aging model. A software stack for VarEMU features precise control over faults and provides virtual energy monitors to the operating system and processes. This allows users to precisely quantify and evaluate the effects of variations on individual applications. We show how VarEMU tracks energy consumption according to variation-aware power and aging models and give examples of how it may be used to quantify how faults in instruction execution affect applications.

A Hierarchical Approach for Power Management on Mobile Embedded Systems

Mobile Embedded Systems usually are simple, battery-powered systems with resource limitations. In some situations, their batteries lifetime becomes a primordial factor for reliability. Because of this, it is very important to handle power consumption of such devices in a non-restrictive and low-overhead way. This power management cannot restrict the wide variety of different low-power modes such devices often feature, thus allowing a wider system configurability. However, once in such devices processing and memory are often scarce, the power management strategy cannot compromise large amounts of system resources. In this paper we propose a simplified interface for power management of software and hardware components. The approach is based on the hierarchical organization of such components in a component-based operating system and allows power management of system components without the need for costly techniques or strategies. A case study including real implementations of system and application is presented to evaluate the technique and shows energy saves of almost 40% by just allowing applications to express when certain components are not being used.

An efficient calibration method for RSSI-based location algorithms

Position awareness is a desirable feature for many applications of Wireless Sensor Networks. The Received Signal Strength Indication of a radio channel provides a feasible way of estimating distance between nodes because its use doesnpsilat require any additional hardware but a radio transceiver. The main drawback of using RSSI is its instability and interference susceptibleness noticed in real environments. This work shows an evaluation of a location algorithm for wireless sensor networks and presents a new calibration approach that substantially improves the trustworthiness in its results. The results show that adequately adjusted RSSI measurements can be successfully used for localization in wireless sensor networks.

Operating Systems Portability: 8 bits and beyond

Embedded software often needs to be ported from one system to another. This may happen for a number of reasons among which are the need for using less expensive hardware or the need for extra resources. Application portability can be achieved through an architecture-independent software/hardware interface. This is not a straight-forward task in the realm of embedded systems, since they often have very specific platforms. This work shows how an application-oriented component-based operating system was developed to allow system and application portability. Case studies present two embedded applications running in different platforms, showing that application source code is totally free of architecture-dependencies

Low-cost estimation of sub-system power

Real-time, fine-grained power consumption information enables energy optimization and adaptation for operating systems and applications. Due to the high cost associated with dedicated power sensors, however, most computers do not have the ability to measure disaggregated power consumption at a component or subsystem level. We present DiPART (Disaggregated Power Analysis in Real Time), a tool to estimate subsystem power consumption based on performance (event) counters and a single, system-wide power sensor. With only one power sensor for overall system power consumption, DiPART is able to self-adapt to variations in subsystem power consumption present across nominally identical hardware. We validate the approach using a cluster of Intel Atom-based nodes that has been instrumented for subsystem (CPU, RAM and disk) power measurements. DiPART was tested across nodes in the cluster using varied benchmarks, resulting in a 40% reduction in estimation error when compared to a static model.

Operating system support for handling heterogeneity in wireless sensor networks

Developments in wireless sensor networks (WSN) hardware have led to a diversity of sensing devices, ranging from simple, micro-controlled boards to complex, highly integrated sensor-transceiver ICs. Given this diversity, the lack of proper abstraction and encapsulation mechanisms at the operating system level often forces developers to reimplement their sensing applications whenever a different sensor, radio or processor is deployed. In this paper we introduce a novel strategy for abstracting wireless sensor networks hardware, implemented for the EPOS operating system. It consists in providing application programmers with a high level interface for sensing components, that can latter be bound to pre-existing components that are adapted on demand at system generation time to fulfill application requirements, thus enabling programmers to code portable sensing applications in spite of the hardware diversity and without significant overhead

Configurable Medium Access Control for Wireless Sensor Networks

This article presents C-MAC, a Configurable Protocol for medium access control in wireless sensor networks. C-MAC works as a framework of medium access control strategies, with a transparent configuration system. The protocol aggregates different services, each implemented in several different strategies. Applications may configure different communication parameters in compile-time and run-time. C-MAC’s metaprogrammed implementation yields smaller footprint and higher performance than equivalent protocols for wireless sensor networks.

Speculative Precision Time Protocol: Submicrosecond clock synchronization for the IoT

Time synchronization is a keystone of Wireless Sensor Networks (WSN). It is fundamental to coordinate the action of nodes in a network and it is also a critical element of several security mechanisms. In this paper, we discuss and evaluate the time synchronization strategy behind the Trustful Space-Time Protocol (TSTP), which explores the protocols cross-layer architecture to speculatively peek through the timestamps and geographic info present in message headers, implementing high-accuracy clock synchronization with minimal insertion of explicit messages. We evaluate the protocol analytically and experimentally. The analytic evaluation is based on the model defined by Schmid [15] for the Virtual High-resolution Time (VHT), while the experimental evaluation was performed on the IEEE 802.15.4-compliant EPOSMote platform running EPOS and TSTP. Our results demonstrate that nodes in the network can be consistently synchronized with sub-microsecond precision while exchanging far less messages than they would with an ordinary, non-speculative implementation, resulting in energy savings. Indeed, precision and energy savings are higher for networks with higher traffic, since more messages are available for peeking. In an experiment scenario in which messages were exchanged between devices every 15 seconds, nodes in the network achieved a synchronization error of approximately 15 microseconds in the worst case, while in a scenario in which messages were exchanged every 3 seconds, synchronization error was less than 0.5 microseconds in the worst case, and approximately 0.25 microseconds on average.