Lucien Johannes Breems

A quadrature data-dependent DEM algorithm to improve image rejection of a complex /spl Sigma//spl Delta/ modulator

A data-dependent DEM algorithm is controlled by the quadrature bitstreams of a complex /spl Sigma//spl Delta/ modulator. The quadrature feedback paths of the modulator are dynamically matched, without increasing the in-band noise. Test chips with an initial 20% mismatch have a typical image rejection ratio of 61 dB with DEM.

IF-to-digital converter for FM/AM/IBOC radio

An IF-to-digital converter that can handle AM, FM, and IBOC (In Band On Channel) signals is presented. The highest radio quality is obtained by a front-end with a single tuner and two IF-to-digital converters for seamless blending between the AM/FM and the IBOC (digital radio) mode. The IF-to-digital converters incorporate mixers that are highly insensitive to parasitic double sampling. Besides the converters the chip includes digital IF post-processing circuitry, three radio DSPs (digital signal processors) and the audio part to fulfill the rest of the car radio functions. Radio functions like signal quality improvement, signal demodulation, weak signal handling, multipath, phase antenna diversity and customer specific features are implemented in software for high system flexibility. The IF-to-digital converter is processed in a 0.18 /spl mu/m CMOS process and achieves 99dB in a 3kHz Am bandwidth, 79dB in the 200kHz FM band and 74dB in 575kHz for IBOC.

Digital Calibration of a Continuous-Time Cascaded ΣΔ Modulator based on Variance Derivative Estimation

This paper presents a digital calibration system for a continuous-time cascaded ΣΔ modulator. The calibration algorithm matches the digital noise cancellation filter coefficients with the integrator time constants of the analog loop filters, resulting in an optimal signal-to-quantization noise ratio. The calibration method that is proposed is based on a two-point variance estimation of the idling output data stream when zero input signals are applied. This calibration is highly insensitive to the large spread of the variance, due to the pseudo random nature of a ΣΔ modulator. The main advantages of this calibration method are the very high accuracy and very fast calibration speed, while the additional hardware costs are negligible. A 0.18mum CMOS prototype test chip has been fabricated and the measured calibration time is 0.6ms for a 10MHz, 67dB dynamic range continuous-time cascaded ΣΔ modulator.

An 8-bit, 4-Gsample/s Track-and-Hold in a 67GHz fT SiGe BiCMOS technology

In this paper we present design and measurements of a high-speed track-and-hold (T&H) circuit. The circuit was implemented in a low-cost 67GHz fT SiGe technology. At 4GS/s the circuit achieves SNR better than 52dB and THD of -50.5dB, corresponding to 8.1 effective bits. This performance is achieved for input frequencies up to 1.1GHz with a differential full-scale input swing of 0.9VPP. The power dissipation of the T&H, including buffers and clock driver, is 590mW. Since measurements at such high frequencies are challenging, a full description of the measurement setup is provided

An 118dB DR CT IF-to-Baseband /spl Sigma//spl Delta/ Modulator for AM/FM/IBOC Radio Receivers

A 1b 51h-order complex CTDeltaSigma modulator with integrated IF mixer for AM/FM/IBOC car radio receivers is presented. The 118dB DR in AM mode enables the realization of the receiver without a VGA and an external AM channel filter. It is fabricated in a 0.18mum CMOS process and consumes 210mW from a 1.8V supply