Luigi Mariucci

High-field-effect-mobility pentacene thin-film transistors with polymethylmetacrylate buffer layer

A thin film of polymethylmetacrylate (PMMA) acting as a buffer layer has been employed in order to fabricate high-quality pentacene thin-film transistors (TFTs), both in bottom contact and top contact configuration. A PMMA buffer layer allows to reduce the interaction between a π-conjugated system of pentacene and the metal or dielectric substrate. We show that a thin PMMA buffer layer improves crystal quality along the metal contacts’ boundaries, while still allowing good ohmic contact. Pentacene TFTs, including a PMMA buffer layer, show very high field-effect mobility, μFE=0.65 and 1.4cm2∕Vs, for bottom and top contact configuration, respectively, and remarkable steep subthreshold region.

Aging effects in pentacene thin-film transistors: Analysis of the density of states modification

Field effect analysis has been employed in order to calculate the density of states of high quality pentacene thin-film transistors. The degradation of the electrical characteristics caused by the exposure to air has been studied and discussed in term of density of states modification. The calculated density of the states has been approximated by two exponential terms, as in amorphous silicon, and it has been used in a two-dimensional numerical simulation in order to reproduce the electrical characteristic variation with respect of the temperature and aging time.

Controlling field-effect mobility in pentacene-based transistors by supersonic molecular-beam deposition

We show that pentacene field-effect transistors, fabricated by supersonic molecular beams, have a performance strongly depending on the precursor’s kinetic energy (KE). The major role played by KE is in achieving highly ordered and flat films. In the range KE≈3.5–6.5eV, the organic field effect transistor linear mobility increases of a factor ∼5. The highest value (1.0cm2V−1s−1) corresponds to very uniform and flat films (layer-by-layer type growth). The temperature dependence of mobility for films grown at KE>6eV recalls that of single crystals (bandlike) and shows an opposite trend for films grown at KE⩽5.5eV.

Analysis of Self-Heating-Related Instability in Self-Aligned p-Channel Polycrystalline-Silicon Thin-Film Transistors

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

Evidence of Correlated Mobility Fluctuations in p-Type Organic Thin-Film Transistors

We report on the results of noise measurements in p-type organic thin-film transistors (TFTs) extending from the subthreshold region into the strong accumulation region over four decades of drain current values. The low-frequency noise produced by the devices can be successfully interpreted in the context of a multitrap correlated number fluctuation-mobility fluctuation (CMF) theory, while neither phonon-induced mobility fluctuation nor carrier number fluctuation mechanisms are capable of justifying the observed noise behavior. The Coulomb scattering parameter is found to be in the order of 107 Vs/C, about three orders of magnitude larger with respect to crystalline silicon MOSFETs and comparable with what already reported in hydrogenated amorphous silicon TFTs, suggesting a much more relevant contribution coming from CMF in disordered materials.

Correlated Mobility Fluctuations and Contact Effects in p-Type Organic Thin-Film Transistors

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/f behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility (μeff ~ 2 cm2/V/s), the large scattering parameter (α ~ 107 Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product αμeff ≈ 2·107 cm2/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

Invited) Short Channel Effects and Drain Field Relief Architectures in Polysilicon TFTs

Applications of polycrystalline silicon (polysilicon) thin film transistors (TFTs) to active matrix organic light emitting displays require further performance improvement. The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6μm to 1μm, or less. However, short channel effects and hot-carrier induced instability in scaled down conventional self-aligned polysilicon TFTs can substantially degrade the device characteristics. To reduce these effects and allow proper operation of the circuits, drain field relief architectures have to be introduced. In this work we show that a fully self-aligned gate overlapped lightly doped drain (LDD) structure, with submicron LDD regions, can provide an excellent solution, allowing effective short channel effect control and improved electrical stability.

Edge Effects in Self-Heating-Related Instabilities in p-Channel Polycrystalline-Silicon Thin-Film Transistors

Self-heating-related instabilities have been investigated in p-channel polycrystalline-silicon thin-fllm transistor, showing an anomalous transconductance (gm) increase. The gm increase is a fingerprint of edge effects, resulting from a buildup of positive trapped charge in the gate oxide at the channel edges. This was confirmed by the annihilation of such positive charges obtained by sequential hot-carrier bias-stress experiments. From the analysis of the edge effects in devices with different channel lengths, we were able, using 2-D numerical simulations, to deter mine the size of the defected edge regions to be 400 nm.

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance-voltage, and noise measurements. Results suggest that transport in the CYTOPTM gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier φB ≈ 1 eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility μθ estimated in the order of 10-9 cm2/(Vs). Gate current noise follows a 1/f law and it is found to be proportional to I2G, which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.