Luis A. Bonet

Test features of the MC145472 ISDN U-transceivers

The design of a single-chip implementation of a 2B1Q ISDN (integrated services digital network) U transceiver that meets the ANSI T1.601 standards has been completed. The MC145472 was designed with testability in mind and to be consistent with Motorolas design-for-manufacturability goals. The authors describe in detail the design-for-testability techniques specifically intended for the IC manufacturer production test and other ad hoc test/diagnostic structures for the customer to use in evaluating system performance. A global test strategy for testing the ISDN U transceiver is presented. The test features have been used extensively not only for testing the device in the production environment but also for conducting evaluations and design verification experiments during the chip debugging phase. The test features described are well integrated with the architecture of the chip, thus minimizing incremental cost.<<ETX>>

Testability features of a 32 kbps ADPCM transcoder

Motorolas MC 145532 ADPCM (adaptive digital pulse-code-modulation) transcoder described is a 16-pin CMOS VLSI application specific digital signal processor (DSP) that implements in full-duplex mode the ANSI (T1.301-1987) standard algorithm for 32-kb/s ADPCM. The application is illustrated of structured test techniques, such as scan path and signature analysis, which are used to enhance the testability of this VLSI signal processor. To perform in real time the numerous computations required by the algorithm, the MC 145532 contains a DSP engine that executes microcode instructions at a 10 MHz rate. The MC145532 was built using 1.5- mu m CMOS technology that has double-level metal capability. The size is roughly 145*210 mils with a transistor count of approximately 50 k transistors.<<ETX>>

A split control store VLSI for 32 kbps ADPCM transcoding

This paper describes the architecture used in a 16 pin CMOS VLSI Digital Signal Processor which was designed by the authors to perform both ANSI and CCITT versions of the ADPCM standard. The part is designed to run from a 20 MHz clock source with an instruction cycle time of 100 ns. This design is a good example of the power of application specific DSP designs to reduce the cost of implementing stable algorithms.