Tim A. Williams

A split control store VLSI for 32 kbps ADPCM transcoding

This paper describes the architecture used in a 16 pin CMOS VLSI Digital Signal Processor which was designed by the authors to perform both ANSI and CCITT versions of the ADPCM standard. The part is designed to run from a 20 MHz clock source with an instruction cycle time of 100 ns. This design is a good example of the power of application specific DSP designs to reduce the cost of implementing stable algorithms.

ISDN U transceiver algorithm, development system, and performance

Motorola and BNR are currently developing the MC145472, a single-chip implementation of a 2B1Q ANSI standard U-interface transceiver for ISDN (integrated services digital network) basic rate access (BRA). The transceiver provides full duplex transmission of 160 kb/s over two-wire nonloaded outside plant loops and is designed to meet the ANSI T1.601 1988 standards for use in both LT and NT1 applications. Its implementation involves state-of-the-art analog and digital signal processing (DSP) technology. The authors describe the functions and verifications of the transceiver, with emphasis on the DSP technology used for echo cancellation, equalization, and timing recovery; the design methodology and hardware testbed used to develop the transceiver algorithms; and performance results for the transceiver under both laboratory and field conditions.<<ETX>>

A systolic IIR decimator

A discussion is presented of several methods of providing complex pole pairs in the transfer function of a decimator for oversampled converters. Utilization of pole cancellation with added compensating zeros yields a systolic structure that is easily implemented. Decomposition of the coefficient terms of the IIR decimator by means of a high radix modified Booths algorithm recording scheme is shown to be efficient. An extension to the Agarwal and Burrus transformation for poles close to the z=1 point on the z-plane is shown to allow a reduction in the precision of the coefficients.<<ETX>>