Lukas Sekanina

Efficient recognition of speed limit signs

An automatic traffic sign detection system is important in a driver assistance system. An approach for detecting Norwegian speed limit signs is proposed. It consists of three major steps: color-based filtering, locating sign(s) in an image and detection of numbers on the sign. About 91% correct recognition is achieved for a selection of 198 images.

Image Filter Design with Evolvable Hardware

The paper introduces a new approach to automatic design of image filters for a given type of noise. The approach employs evolvable hardware at simplified functional level and produces circuits that outperform conventional designs. If an image is available both with and without noise, the whole process of filter design can be done automatically, without influence of a designer.

An evolvable hardware system in Xilinx Virtex II Pro FPGA

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution by Martinek and Sekanina, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 sec in average.

Novel Hardware Implementation of Adaptive Median Filters

A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300 M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%. In addition to filtering, adaptive median filters can be also used as detectors of corrupted pixels (detection statistics).

Evolutionary design of gate-level polymorphic digital circuits

A method for the evolutionary design of polymorphic digital combinational circuits is proposed. These circuits are able to perform different functions (e.g. to switch between the adder and multiplier) only as a consequence of the change of a sensitive variable, which can be a power supply voltage, temperature etc. However, multiplexing of standard solutions is not utilized. The evolved circuits exhibit a unique structure composed of multifunctional polymorphic gates considered as building blocks instead. In many cases the area-efficient solutions were discovered for typical tasks of the digital design. We demonstrated that it is useful to combine polymorphic gates and conventional gates in order to obtain the required functionality.

An evolvable image filter: experimental evaluation of a complete hardware implementation in FPGA

This paper describes an evolvable image filter which is completely implemented in a field programmable gate array. The proposed system is able to evolve an image filter in a few seconds if corrupted and original images are supplied by user. The architecture is generic and can easily be modified to realize other evolvable systems. COMBO6 card with Xilinx Virtex xc2v3000 FPGA is used as a target platform.

Evolutionary Approach to Approximate Digital Circuits Design

In approximate computing, the requirement of perfect functional behavior can be relaxed because some applications are inherently error resilient. Approximate circuits, which fall into the approximate computing paradigm, are designed in such a way that they do not fully implement the logic behavior given by the specification and, hence, their accuracy can be exchanged for lower area, delay or power consumption. In order to automate the design process, we propose to evolve approximate digital circuits that show a minimal error for a supplied amount of resources. The design process, which is based on Cartesian genetic programming (CGP), can be repeated many times in order to obtain various tradeoffs between the accuracy and area. A heuristic seeding mechanism is introduced to CGP, which allows for improving not only the quality of evolved circuits, but also reducing the time of evolution. The efficiency of the proposed method is evaluated for the gate as well as the functional level evolution. In particular, approximate multipliers and median circuits that show very good parameters in comparison with other available implementations were constructed by means of the proposed method.

On routine implementation of virtual evolvable devices using COMBO6

This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification. The approach generates the implementation of a virtual reconfigurable circuit and evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3 - 3-bit multipliers. The COMBO6 card is employed for these experiments.

Evolutionary Design of Arbitrarily Large Sorting Networks Using Development

An evolutionary algorithm is combined with an application-specific developmental scheme in order to evolve efficient arbitrarily large sorting networks. First, a small sorting network (that we call the embryo) has to be prepared to solve the trivial instance of a problem. Then the evolved program (the constructor) is applied on the embryo to create a larger sorting network (solving a larger instance of the problem). Then the same constructor is used to create a new instance of the sorting network from the created larger sorting network and so on. The proposed approach allowed us to rediscover the conventional principle of insertion which is traditionally used for constructing large sorting networks. Furthermore, the principle was improved by means of the evolutionary technique. The evolved sorting networks exhibit a lower implementation cost and delay.

Towards evolvable IP cores for FPGAs

The paper deals with a new approach to the design of adaptive hardware using common field programmable gate arrays (FPGA). The ultimate aim is to develop evolvable IP (intellectual property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware.