Lung-Tien Liu

Circuit Partitioning for Huge Logic Emulation Systems

Given a huge system represented at gate level, we propose an algorithm mapping the design into the minimum number of FPGAs for logic emulation. We first devise a Local Ratio-cut clustering scheme to reduce the circuit complexity. Then a Set Covering partitioning approach, utilizing the paradigm of Espresso II, is proposed to replace the widely adopted recursive partitioning paradigm. Experimental results show that our approach achieves significant improvement in a much shorter run time compared to the recursive Fiduccia-Mattheyses approach on large designs. For example, on a benchmark of 160K gates and 90K nets, we reduced the number of FPGAs required by 29% and reduced the run time by 78%.

A replication cut for two-way partitioning

Graph partitioning is crucial in multiple-chip design, floorplanning and mapping large logic networks into multiple FPGAs. Replication logic can be used to improve the partitioning. Given a network G with only two-pin nets and a pair of nodes s and t to be separated, we introduce a replication graph and an O(mn log(n/sup 2//m)) algorithm for optimum partitioning with replication and without size constraints, where m and n denote the number of nets and the number of nodes in G, respectively. In VLSI designs, each partition has size constraints and the given network contains multiple-pin nets. A heuristic extension is adopted to construct replication graphs with multiple-pin nets. Then we use a directed Fiduccia-Mattheyses algorithm in the constructed replication graph to solve the replication cut problem with size constraints. >

A gradient method on the initial partition of Fiduccia-Mattheyses algorithm

In this paper, a Fiduccia-Mattheyses (FM) algorithm incorporating a novel initial partition generating method is proposed. The proposed algorithm applies to both bipartitioning and multi-way partitioning problems with or without replication. The initial partition generating method is based on a gradient descent algorithm. On partitioning without replication, our algorithm achieves an average of 17% improvement over the analytical method, PARABOLI, on bipartitioning, 10% better than Primal-Dual method on 4-way partitioning and 51% better than net-based method. On partitioning allowing replication, our algorithm achieves an average of 23% improvement over the directed Fiduccia-Mattheyses algorithm on Replication Graph (FMRG) method on bipartitioning.

Unified quadratic programming approach for mixed mode placement

A complete placement system, UPlace, for mixed mode designs is presented, which consists of a force-directed global placement, and a zone-refinement based detailed placement. For global placement, a unified objective function capturing both wire length and cell distribution is proposed; quadratic programming is formulated to optimize the unified object function efficiently; a discrete cosine transformation method is devised to calculate the uneven cell distribution cost. A dynamic approach for decomposing multi-pin nets into two-pin nets is also introduced for better wire length modeling. Zone refinement method is used for a unified legalization and detailed placement process. Experimental results show that the placement algorithm is very promising.

Performance-driven partitioning using retiming and replication

We propose a novel paradigm for two-way circuit partitioning which minimizes the clock cycle. The replication technique is suggested for feedback loops to minimize the impacts of intermodule delays and the crossing edges when necessary. A flow timing cut is devised to produce partitions which can be guaranteed to achieve clock cycles equal to their lower bound with respect to the partitions using retiming. When the clock cycle optimization is the major objective and feedback loop sizes are not large, we propose an efficient, easy to implement algorithm which still guarantees achieving the lower bound clock cycle with respect to its partition. Experimental results have shown that our algorithms can achieve an average of 15% clock cycle time reduction compared to the best retimed results produced by 20 runs on each test case using a Fiduccia-Mattheyses algorithm.

Performance-Driven Partitioning Using a Replication Graph Approach

An efficient algorithm is proposed to tackle the performance-driven partitioning problem using retiming and replication. We devise a replication graph to model the composite effect of replication and retiming. With the replication graph, we formulate the problem as an integer linear programming problem. A heuristic algorithm is derived to solve the problem by exploring the dual program of its linear programming relaxation.

Local ratio cut and set covering partitioning for huge logic emulation systems

Given a system represented at gate level, we propose an algorithm mapping the design into the minimum number of FPGAs for logic emulation. We first devise a Local Ratio-cut clustering scheme to reduce the circuit complexity. Then a Set Covering partitioning approach, utilizing the paradigm of Espresso II, is proposed as an alternative to the widely adopted recursive partitioning paradigm. Experimental results have shown that our approach achieved significant improvement with much shorter run times compared to the recursive Fiduccia-Mattheyses approach on large designs. For instance, on a benchmark of 160 K gates and 90 K nets, we reduced the number of FPGAs required and the run time by 41 and 86%, respectively. >

Incremental physical resynthesis for timing optimization

This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and physical optimizations without incurring unmanageable runtime complexity. Unlike previous approaches to this problem which limit the types of operations and/or architectural features, we take advantage of many architectural characteristics of modern FPGA devices, and utilize many types of optimizations including cell repacking, signal rerouting, resource retargeting, and logic restructuring, accompanied by efficient incremental placement, to gradually transform a design via a series of localized logic and physical optimizations that verifiably improve overall compliance with timing constraints. This procedure works well on small and large designs, and can be administered through either an automatic optimizer, or an interactive user interface. Our preliminary experiments showed that this approach is very effective in fixing or reducing timing violations that cannot be reduced by other optimization techniques: For a set of test cases to which this is applicable, the worst timing violation is reduced by an average of 42.8%.

Finite state machine decomposition for I/O minimization

In this paper, we consider the problem of decomposing a Finite State Machine (FSM) into communicating FSMs to minimize the number of inputs/outputs. We propose an FSM decomposition procedure based on partitioning the set of transitions that describes the behavior of an FSM. An extended FM-based partitioning algorithm is applied for transition partitioning. We also devise a state output encoding technique to further reduce the number of interconnections between the FSMs required for communication. Experimental results for MCNC benchmarks show that our algorithm has favorable results over circuit partitioning algorithms on the netlist level.

Network partitioning into tree hierarchies

This paper addresses the problem of partitioning a circuit into a tree hierarchy with an objective of minimizing a global interconnection cost. An efficient and effective algorithm is necessary when the circuit is huge and the tree has many levels of hierarchy. We propose a heuristic algorithm for improving a partition with respect to a given tree structure. The algorithm utilizes the tree hierarchy as an efficient mechanism for iterative improvement. We also extend the tree hierarchy to apply a multi-phase partitioning approach. Experimental results show that the algorithm significantly improves the initial partitions produced by multiway partitioning and by recursive partitioning.