Lydia L. W. Leung

Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-/spl mu/m-in diameter on 400-/spl mu/m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-/spl mu/m via, the inductance and resistance are measured to be 254 pH and 0.1 /spl Omega/, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.

Low-loss coplanar waveguides interconnects on low-resistivity silicon substrate

This paper describes fabrication, characterization and simulation of low-loss coplanar waveguide (CPW) interconnects on low-resistivity silicon substrate. The fabrication of CPWs is low-temperature (below 250/spl deg/C) and incorporates a spin-on low-k dielectric benzocyclobutene (BCB) and self-aligned electroplating of copper. The performance of CPWs is evaluated by high-frequency characterization and EM simulation. CPWs with different line width (W) and line spacing (S) are investigated and compared. Using a BCB layer as thick as 20 /spl mu/m, CPW fabricated on a low-resistivity silicon substrate exhibits an insertion loss of 3 dB/cm at 30 GHz.

CMOS-compatible micromachined edge-suspended spiral inductors with high Q-factors and self-resonance frequencies

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.

Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB/lambdag) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed

CMOS-compatible micromachining techniques for fabricating high-performance edge-suspended RF/microwave passive components on silicon substrates

This paper reports the micromachining techniques for fabricating edge-suspended RF/microwave passive components, which are proposed to deliver enhanced performance without sacrificing their mechanical strength and reliability. The fabrication incorporates ICP-DRIE dry etching and TMAH anisotropic etching techniques, which are both CMOS compatible. The edge-suspended structures were realized by a TMAH solution consisting of 5 wt% TMAH, 1.6 wt% Si and 0.5 wt% (NH4)2S2O8. This solution offers effective etching of silicon along the {100} and {110} planes, while having negligible etching on aluminum and {111} planes. The layout requirement for achieving edge-suspended passive components is also outlined on the basis of the analysis of the anisotropic etching along different crystal orientations. Using the techniques described here, high performance spiral inductors and coplanar waveguides (CPW) with significantly reduced loss are demonstrated. For a three-turn 4.5 nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 GHz to 14.3 GHz) in self-resonance frequency are obtained with an 11 µm suspended edge in 25 µm wide lines compared to the conventional inductors without being micromachined. A 50 Ω edge-suspended CPW exhibits a reduction in insertion loss, from 2.4 dB mm−1 in a conventional CPW to 0.4 dB mm−1 at 39 GHz.

Microwave characterization of high aspect ratio through-wafer interconnect vias in silicon substrates

In this paper, we present detailed fabrication process and high-frequency characterization of through-wafer copper-filled via holes ranging from 40 /spl mu/m to 70 /spl mu/m in diameter on 400 /spl mu/m-thick silicon substrates. The high aspect ratio via holes are achieved by carefully tuning the inductively coupled plasma (ICP) etching process and the high aspect ratio via holes are filled completely using a bottom-up electroplating approach. The fabricated via holes were characterized using different resonating structures and the measured inductance and resistance of the 70 /spl mu/m via are 409 pH and 0.154/spl Omega/ respectively. In addition, the effect of the via arrangement on the resulting inductance are also evaluated.

On-Chip Microwave Filters on Standard Silicon Substrate Incorporating a Low-k BCB Dielectric Layer

A low-loss, low-pass microstrip transmission line based microwave filter using 6-¿m low-k dielectric, Benzocyclobutene (BCB), as an interface layer has been fabricated on a standard CMOS grade silicon substrate. Standard 50-Ohm microstrip lines were fabricated and exhibit lower loss compared with the microtrip line on silicon without the BCB layer. The filter has a cut-off frequency at 10 GHz with an insertion loss of 1.1 dB. Simulation and measurement results of the filter are provided. Full-wave analysis of a 10 GHz bandpass filter is shown as well.

CAD equivalent-circuit modeling of attenuation and cross-coupling for edge-suspended coplanar waveguides on lossy silicon substrate

In this paper, a compact computer-aided design (CAD)-oriented frequency-independent equivalent-circuit model, taking the skin effect, proximity effect, and substrate effect into consideration, is presented for the edge-suspended coplanar waveguide (ESCPW) on lossy silicon substrate. The ESCPWs exhibit the benefit of reduced loss, while avoid the reliability issues that are associated with the suspended coplanar waveguides. The model shows good agreement with the measured insertion loss and the extracted RLGC line parameters up to 25 GHz. With the model, the relationship between physical perimeters of the ESCPWs and the electrical characteristics is also investigated. Moreover, cross-coupling between adjacent ESCPWs with common ground is characterized and modeled.

High-Q CMOS-compatible micromachined edge-suspended spiral inductors

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are realized using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. Since the coupling to the low resistivity silicon substrate is dominated by the current carrying parts (the edges), the substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membrane or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The edge-suspension structures are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor, a 57% increase (from 9.1 GHz to 14.3 GHz) in self-resonance frequency are obtained with a 11 /spl mu/m suspended edge in 25 /spl mu/m wide lines.

High-performance microwave passive components on silicon substrate

High-Performance microwave passive components are demonstrated on standard silicon substrate incorporating a low-k Benzocyclobutene (BCB) layer. Metal ohmic loss and substrate coupling loss, the two major factors that degrade the on-chip passive components are suppressed by the employment of electroplated copper and the low-k BCB layer, respectively. Spiral inductors exhibit Q-factor as high as 25 at 2 GHz. A low-loss, low-pass microstrip transmission line based microwave filter has been fabricated. The filter has a cut-off frequency at 10 GHz with an insertion loss of -1.1 dB. The fabrication process is low-cost and low-temperature, making it suitable for post-IC process for high performance RFICs and MMICs.