Philip C. H. Chan

SOI thermal impedance extraction methodology and its significance for circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R/sub th/) and thermal capacitance (C/sub th/) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits.

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

The threshold voltage, V/sub th/, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V/sub th/ roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, /spl Delta/V/sub th/ is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V/sub th/ design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V/sub th/ design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained. >

An improved TMAH Si-etching solution without attacking exposed aluminum

In this paper, an improved Tetramethyl Ammonium Hydroxide (TMAH) etching method is reported. The process features higher silicon etching rate and results in smooth silicon surface and at the same time, no significant aluminum etching is observed. We believe that after TMAH etching the aluminum surface is protected by the coating of by-products, which prevents etching of the underlying aluminum films by the TMAH solution. The etchant used in the study consists of 5 wt.% TMAH solution, 1.4 wt.% (or above) dissolved silicon, and 0.4-0.7 wt.% (NH/sub 4/)/sub 2/S/sub 2/O/sub 8/ oxidant additive. Silicon etching rate of 0.9-1.0 /spl mu/m/min and zero aluminum etching rate is be achieved using the process. Moreover the silicon surface remains smooth after etching. The etching process demonstration in this work is readily applicable to MEMS device fabrication such as polysilicon like sacrificial layer removal after metallization is completed.

Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer.

Thermal analysis and design of a micro-hotplate for integrated gas-sensor applications

Abstract The application of commercial mechanical computer-aided engineering (MCAE) software to the design and analysis of micro-hotplate (MHP) structures is presented. The simulation provides an estimation of heating efficiency and temperature distribution on the hotplate. The analysis is applied to a newly proposed MHP structure during layout design. Novel design results in a hotplate with high heating efficiency, good temperature uniformity and ease of temperature sensing. The simulation result has been compared with experimental measurement. For the first time, liquid crystal thermography is used to visualize the temperature profile on the hotplate.

A low-power CMOS compatible integrated gas sensor using maskless tin oxide sputtering

Abstract This paper describes a CMOS compatible integrated gas sensor. The device was designed so that the front-end fabrication is fully compatible with the standard CMOS process. The non-CMOS compatible fabrication steps were carried out as post-processing steps. This included the silicon anisotropic etch to create the thermally isolated micro-hotplate (MHP) and the deposition of gas-sensitive thin films using maskless r.f. SnO 2 sputtering. The sensors exhibited high sensitivities to gases, such as ethanol and hydrogen.

A wide tuning range gated varactor

A wide tuning range gated varactor for radio frequency (RF) applications is described in this paper. The gated varactor is a three-terminal device. The third terminal helps achieve an improved tuning range. The measured tuning range of the varactor exceeds /spl plusmn/50%. The new device can be implemented with a standard CMOS process without any post-processing. A 2 GHz prototype voltage-controlled oscillator (VCO) is implemented using the new varactor in a 0.35-/spl mu/m CMOS process. The VCO achieved a sensitivity of 220 MHz/V.

Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size.

Self-heating characterization for SOI MOSFET based on AC output conductance

A simple and accurate characterization method for the self-heating effect in SOI MOSFET is reported for the first time. The AC output conductance at one bias point and several frequencies are measured to determine the thermal resistance (R/sub th/) and thermal capacitance (C/sub th/) associated with SOI devices. The proposed methodology is critical for removing the misleadingly large self-heating effect from the DC I-V data in device modeling.

Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET's

Floating-body partially depleted (PD) SOI MOSFETs exhibit excess low-frequency noise. For the first time, the origin of the excess noise is identified to be the shot noise associated with impact ionization current and body-source diode current. The shot noise, normally negligible as compared with flicker noise, is amplified in the device through the floating-body effect (FEE). A physically-based noise model is proposed which predicts that the excess low-frequency noise shows a Lorentzian-like spectrum as verified by experimental data. The physical explanation is further supported by the coincidence of the characteristic frequency in noise spectrum and AC output impedance of the device.