M.A. Al-Turaigi

Current-mode precision rectification

This paper describes a simple and versatile current-mode full-wave precision rectifier circuit using AD844 from Analog Devices. The proposed scheme avoids the use of closely matched resistors and matched current mirrors. The circuit is easy to design and construct from readily available low-cost components and provides excellent precision rectifier performance over a wide band and wide input voltage range. Experimental results are included.

An improved current-mode instrumentation amplifier with bandwidth independent of gain

A modification in current-mode instrumentation amplifier topology proposed in Electronics Letters, vol. 25, p.470-471 (1989) is described, and a detailed analytical analysis is given to show its superiority. The proposed circuit design is simple and easy to construct from readily available IC AD844 from Analog Devices. The proposed circuit features high CMRR without requiring well-matched resistors. Moreover, high differential gain and bandwidth can be achieved simultaneously. Experimental as well as simulation results are given in support of theoretical conclusions. >

Operational floating current conveyor: characteristics, modelling and applications

A new five-port general purpose analogue building block, termed as an operational floating current conveyor (OFCC), is described. The OFCC combines the features of current feedback (CFB) operational amplifier, second generation current conveyor and operational floating conveyor (OFC). A simple implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working model. The OFCC is then used as a single block to realize the four main amplifier types and the current conveyors (CCII+ and CCII-). Computer simulation results are presented and discussed.<<ETX>>

Linearized thermistor thermometer using an analog multiplier

A scheme using an analog multiplier that provides an output voltage linearly proportional to the absolute temperature over a wide dynamic range is presented. It has the advantage of being simple and attractive in that the calibration of the output indicating meter does not depend upon the thermistor parameters. Results of measurements in the range 283-493 K are presented. The deviation from the straight-line response amounts to an error of 6% at 283 K and decreases to about 0.6% at 320 K. >

A novel wide range linearization approach for thermistor thermometer

A logarithmic function for response linearization of the thermistor thermometer is presented. A theoretical study of the proposed scheme is presented. A novel and inexpensive circuit configuration for realizing the proposed logarithmic function is described. The approach offers linear temperature/voltage conversion over a wide dynamic range with an output that is independent of fluctuations in the ambient temperature. Test results are given to support the theoretical conclusions.

A fast VLSI system for computing third order cumulants

A fast concurrent system for computing third order cumulants is presented. The system consists of (q + 1)(q + 2) processing elements (PEs), where q is the maximum lag of third order cumulant sequence. A huge saving in computation time compared to sequential computation is realized. The system performance in terms of the speedup and efficiency is evaluated. The system is suitable for VLSI implementation.

Computer simulation of a packet switching computer network

Abstract This paper is concerned with using digital computer simulation for the investigation of a possible packet switching computer network for the Saudi Seaports Authority. The paper presents a flexible computer network model for this purpose, and describes how it has been transformed into computer code using the computer language Pascal. The main network variable considered in the investigation is the topology, with three different topologies considered. The first is based on the star topology, while the other two are of different mesh structures. For each topology, the simulation results produced include: the average packet delay, the buffer requirements per node, and the average number of nodes passed by a packet through the network. In addition, the reliability and cost of each topology have been taken into account.

PASCAL simulation for packet switching computer networks

Abstract This paper is concerned with the development of modular PASCAL simulation tools for the investigation of packet switching computer networks. For this purpose, the paper presents a flexible packet switching network model in terms of structure, performance measures, activities and timing rules. The paper describes how this model has been transformed into PASCAL code, making use of PASCAL special features. To illustrate the use of the resulting tools, the paper presents an investigation of a simple packet switching network of three nodes. The tools would be useful to students and researchers in the field.

Transputer arrays for solving partitioned systems of linear equations

In the modelling and analysis of electronic networks one has to deal with large sets of linear equations. Many advances have been reported in the last two decades applying parallel algorithms for the analysis of these equations. Unfortunately most of these algorithms were impractical at the time, being implemented on conventional sequential media. Recently with the evolution of the new concurrent programming language Occam and its hardware realization in the transputer, many of these algorithms can now be modified and run in truly fast parallel-processing media. In this paper an algorithm based on a cellular array of nine cells, working in parallel, is used to solve a partitioned system of N linear equations (with N a multiple of 3). The algorithm is implemented in the Occam programming language using an array of transputers, each representing one cell. The system is driven by one transputer connected to the centre node, responsible for submitting the partitions of the matrix to the cellular array.

A VLSI system to speedup the measurement of the system frequency

One of the approaches to measure the power system frequency is by the least squares method. This method involves huge computation, which is time consuming using a general purpose microprocessor-based system. In this paper, a parallel processing system to speedup the computation of frequency is introduced. The operation and the structure of the array is explained. The size and the computation time of the system are evaluated. It is shown that the proposed system speeds up the computation by at least two orders of magnitude. The system is well suited for VLSI implementation.