Abdul Rahman M. Alamoud

A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current (ION) and ION/IOFF have increased by 225 and 65×, respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency (fT) in the proposed SE-SB-MOSFET (~200 GHz) has increased by 200× as compared with the conventional SB-MOSFET (~1 GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay (65×) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.

VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review

A contributory paper on the study of VLSI architectures of various fuzzy processors and controllers designed for various applications is presented. The paper focuses on the study of VLSI implementation of fuzzy logic hardware to result in small silicon area, high speed of operation and adaptability to different application domains. This paper reviews the circuit and architecture level designing of various components of the fuzzy processors, such as, fuzzifiers, defuzzifiers, inference and rule base. A comparative analysis of the performance of these components has been performed. It is observed that there is a scope for further improvement in terms of power consumption, speed of operation, area and redundancy in these fuzzy processors. Further, from the study it is seen that the design emphasis should be more on inference engine performance and defuzzification units, because of the complexity of computations handled by them. The optimization in these units results in a significant improvement in the overall performance of the system.

Linearized thermistor thermometer using an analog multiplier

A scheme using an analog multiplier that provides an output voltage linearly proportional to the absolute temperature over a wide dynamic range is presented. It has the advantage of being simple and attractive in that the calibration of the output indicating meter does not depend upon the thermistor parameters. Results of measurements in the range 283-493 K are presented. The deviation from the straight-line response amounts to an error of 6% at 283 K and decreases to about 0.6% at 320 K. >

A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree MD between the fuzzified input and the antecedent membership functions MF has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MFs, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.

Hardware realization of Walsh functions and their applications using VHDL and reconfigurable logic

Orthogonal functions/transforms such as Rademacher functions and Walsh functions find extensive use in Scientific and Engineering applications. Software realization of such functions has been common for quite some time. However, hardware realization has distinct advantages and is now feasible and economically viable due to advancements made in the Microelectronics technology. Rademacher functions and Walsh functions have therefore been realized using high level design techniques targeted to Xilinx FPGAs. The application of these functions in generating digital and analog sinusoidal waves on the same chip has been demonstrated.

Interconnect optimization to enhance the performance of subthreshold circuits

Subthreshold circuits are shown to be the best candidate for satisfying the ultra-low power demand of battery-operated systems having moderate throughput. However, exponential increase in driver resistance in subthreshold region and increased global interconnect capacitance will become a major hurdle in improving the speed of subthreshold interconnects. Improving the speed of such low power circuits is a major design challenge in ultra low power domain. This paper presents a comprehensive analysis of Cu and mixed CNT bundle interconnects and investigates their performance in terms of delay and energy delay product (EDP) for future subthreshold circuits. This paper mainly contributes towards optimizing the geometrical (aspect ratio scaling) and process parameters of interconnects especially for subthreshold circuits to increase their speed. Crosstalk analysis has also been carried out with the proposed interconnect geometrical parameters. It has been found that aspect ratio scaling significantly reduces the interconnect delay and switching energy and at minimum aspect ratio, Cu wire performs better than even an optimized mixed CNT bundle for global interconnect length under subthreshold conditions.

A novel wide range linearization approach for thermistor thermometer

A logarithmic function for response linearization of the thermistor thermometer is presented. A theoretical study of the proposed scheme is presented. A novel and inexpensive circuit configuration for realizing the proposed logarithmic function is described. The approach offers linear temperature/voltage conversion over a wide dynamic range with an output that is independent of fluctuations in the ambient temperature. Test results are given to support the theoretical conclusions.

Design and Comparative Analysis of High Performance Carbon Nanotube-Based Operational Transconductance Amplifiers

In this paper, novel carbon nanotube (CNT) based operational transconductance amplifiers (OTAs) have been designed and simulated. Three types of CNT-based OTAs have been designed at 45 nm technology node and have been compared with the conventional CMOS-based OTA. The comparative analysis of the key characteristics of all the devices has revealed that a significant improvement in performance is observed in the CNT-based OTAs, particularly in a pure CNT-OTA. In the pure CNT-OTA, DC gain has increased by 218%, slew rate has increased by 22.58%, the output resistance has increased by 55.2% and the power consumption is ∼ 193 times less in comparison to the conventional CMOS-OTA. Further, common mode rejection ratio (CMRR) and power supply rejection ratio positive (PSRR+) has increased by 31.87% and 136.3%, respectively in pure CNT-OTA. The performance of CNT-based OTAs has also been studied thoroughly by varying the number of CNTs (N), CNT pitch (S) and the diameter of CNTs (DCNT) at 0.9 V. It has been observed that their performance can be improved further by using optimized values of CNT number; inter CNT-pitch and diameter. The stability analysis has shown that the pure CNT-OTA is highly stable. A 16.7% and 4% increase in phase and gain margins is achieved in the pure CNT-OTA in comparison to the bulk CMOS OTA. Finally, band and high pass filters have been realized by using the proposed CNT-based OTAs.

Hybrid AlGaN/GaN high-electron mobility transistor: design and simulation

In this study, the authors propose a novel structure of high-electron mobility transistor (HEMT) with significantly improved performance. The novelty of the proposed HEMT is the realisation of two parallel induced electron layers under the source and drain electrode, one in the form of two-dimensional (2D) electron gas (2DEG) and the other in the form of charge plasma electron gas (CPEG). The proposed device is a hetrostructure GaN/AlGaN device, therefore, a 2DEG gets created. However, two metal electrodes at the source and drain terminals are used in the proposed device, which induce CPEG in an undoped AlGaN film under the source and drain electrode. Therefore, the proposed HEMT device is hybrid and has a combination of CPEG and the 2DEG. A two-dimensional (2D) calibrated simulation study of the proposed device has revealed that its hybrid nature has improved its performance significantly in comparison to the conventional HEMT device having 2DEG only. It has been observed that the ON current has enhanced by 115%, transconductance ( g m ) by 168%, cutoff frequency ( f T ) by 71% and maximum oscillation frequency ( f max ) by 65% in comparison to the conventional HEMT.

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

This research is about a new approach, which is used for optimizing multipliers designs, which are based on the concept of Vedic mathematics. The design has been targeted to to FPGAs (state-of-the art field-programmable gate arrays). It has been assessed that the multiplier produces partial products by utilizing Vedic mathematics concept by deploying basic 4 × 4 multipliers, which is designed by exploiting special features of multiplexers and 6-input look up tables (LUTs) on the same slices, resulting in considerable minimization in area. The multiplier has been realized on Xilinx® Virtex-5 FPGAs. It is significant to notice that pipeline adders were used to obtain final products. Furthermore, the multiplier is developed and organized by using pipeline schemes, which contribute to the enhancement of operating frequency of the multiplier. The results show that the 32-bit pipeline multiplier can work up to a clock frequency of 450MHz. It has utilized 514 slices and 1157 flip-flops and has much less dynamic power than the other reported work.