M. A. Capano

2.6 kV 4H-SiC lateral DMOSFETs

A 4H-SiC lateral double-implanted metal-oxide-semiconductor (LDMOS) field effect transistor is fabricated in a lightly doped n-epilayer on an insulating 4H-SiC substrate. After depleting through the epilayer, the depletion region continues to move laterally toward the drain. The result is an increase in blocking voltage compared to a vertical DMOSFET fabricated in the same epilayer on a conducting substrate. A blocking voltage of 2.6 kV is obtained, nearly double the highest previously demonstrated blocking voltage for a SiC MOSFET.

Observation of quantum-Hall effect in gated epitaxial graphene grown on SiC (0001)

Epitaxial graphene films examined were formed on the Si-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. A high-k gate stack on the epitaxial graphene was realized by inserting a fully oxidized nanometer thin aluminum film as a seeding layer, followed by an atomic-layer deposition process. The electrical properties of epitaxial graphene films are retained after gate stack formation without significant degradation. At low temperatures, the quantum-Hall effect in Hall resistance is observed along with pronounced Shubnikov–de Haas oscillations in diagonal magnetoresistance of gated epitaxial graphene on SiC (0001).

High-voltage (3 kV) UMOSFETs in 4H-SiC

Vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) in 4H-SiC having both trench oxide protection and junction termination extension (JTE) are reported for the first time. Devices are fabricated with and without counter-doped channels. Blocking voltages and specific on-resistances are 3360 V and 199 m/spl Omega/-cm/sup 2/ for doped-channel FETs and 3055 V and 121 m/spl Omega/-cm/sup 2/ for FETs without doped channels. These blocking voltages are the highest reported to date for UMOSFETs in SiC.

Magnetoconductance oscillations in graphene antidot arrays

Epitaxial graphene films have been formed on the C-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. Nanoscale square antidot arrays have been fabricated on these graphene films. At low temperatures, magnetoconductance in these films exhibits pronounced Aharonov–Bohm oscillations with the period corresponding to magnetic flux quanta added to the area of a single antidot. At low fields, weak localization is observed and its visibility is enhanced by intervalley scattering on antidot edges. At high fields, we observe two distinctive minima in magnetoconductance, which can be attributed to commensurability oscillations between classical cyclotron orbits and antidot array. All mesoscopic features, surviving up to 70K, reveal the unique electronic properties of graphene.

Annealing of ion implantation damage in SiC using a graphite mask

For p-type ion implanted SiC, temperatures in excess of 1,600 C are required to activate the dopant atoms and to reduce the crystal damage inherent in the implantation process. At these high temperatures, however, macrosteps (periodic welts) develop on the SiC surface. In this work, the authors investigate the use of a graphite mask as an anneal cap to eliminate the formation of macrosteps. N-type 4H- and 6H-SiC epilayers, both ion implanted with low energy (keV) Boron (B) schedules at 600 C, and 6H-SiC substrates, ion implanted with Aluminum (Al), were annealed using a Graphite mask as a cap. The anneals were done at 1,660 C for 20 and 40 minutes. Atomic force microscopy (AFM), capacitance-voltage (C-V) and secondary ion mass spectrometry (SIMS) measurements were then taken to investigate the effects of the anneal on the surface morphology and the substitutional activation of the samples. It is shown that, by using the Graphite cap for the 1,660 C anneals, neither polytype developed macrosteps for any of the dopant elements or anneal times. The substitutional activation of Boron in 6H-SiC was about 15%.

N-channel 3C-SiC MOSFETs on silicon substrate

Inversion-mode, n-channel 3C-SiC MOSFETs have been fabricated in a 3C-SiC epilayer grown on a 2°-off-axis Si(001) substrate with optimized SiC processing techniques. Phosphorus implantations are employed for source/drain formation and a sheet resistance of 70 Ω per square is obtained after annealing at 1250°C for 30 min in argon. Both drain characteristics and subthreshold characteristics show typical transistor behavior with an effective channel mobility of 165 cm2/Vs. The breakdown field of the gate oxide is about 3.5 MV/cm.

Inversion channel MOSFETs in 3C-SiC on silicon

Abstract : As a substrate material, single crystal SiC wafers are commercially available in diameters up to 75 mm, whereas silicon wafers a?e available in diameters of 200-300 mm. SiC wafers remain quite expensive compared to silicon, and contain%troublesome densities of micropipes that limit the yield of large devices. In the past, several groups have attempted to circumvent these problems by fabricating devices in 3C-SiC films grown epitaxially on silicon substrates, with limited success. However, in this paper we report new results demonstrating high quality inversion channel MOSFETs in 3C-SiC films on silicon. The inversion channel mobility of SiC MOSFETs has been limited to < 50 cm2JVs in the 4H polytype and < 100 cm2fVs in the 6H polytype by a high density of interface states in the upper half of the bandgap. Because of its narrower bandgap, the 3C polytype of SiC is expected to have lower interface state density, leading to higher channel mobilities. We fabricated lateral n-channel MOSFETs in 6 pin p-type epilayers of 3C-SiC grown on 20 off-axis Si(001) substrates. The epilayers were subsequently polished to improve surface smoothness, leaving a 3 %im layer. Sacrificial oxidation was then performed to remove damage caused by polishing. Source and drains were formed by implanting phosphorus and activating at 1250 0C for 30 minutes in argon. The gate oxide was formed by wet oxidation at 1150 0C for 30 minutes, followed by re-oxidation in wet O2 at 950 0C for two hours. A polysilicon gate was deposited by LPCVD and doped by spin-on dopant. Ohmic contacts are unannealed nickel. The resulting MOSFETs show excellent transistor behavior, with good current saturation, a threshold voltage of 1.6 V, and a peak channel mobility of 170 cm2/Vs.

Ion Implantation and 1 MeV Electron Irradiation of 4H-SiC---Comparison Studies

Argon ions (Ar + ) were implanted into n-type 4H-SiC epitaxial layers at 600 °C. The energy of the ions was 160 keV and at a dose of 2 × 10 16 cm −2 . After post-implantation annealing at 1600 °C, Schottky diodes were fabricated on the ion implanted samples. Bulk n-type 4H-SiC samples were irradiated at room temperature with 1 MeV electrons at doses of 1 × 10 16 to 5.1 × 10 17 el/cm 2 . The current density of the beam was 0.91 μA/cm 2 . Deep Level Transient Spectroscopy (DLTS) was used to characterize the induced defects. DLTS studies of Ar + implanted samples showed six defect levels at E C – 0.18 eV, E C – 0.23eV, E C – 0.31eV, E C – 0.38 eV, E C – 0.72 eV, and E C – 0.81 eV. Z1/Z2 defect is the dominant defect in the electron irradiated sample and anneals out completely after 10 minutes at 1000 °C. However, Z1/Z2 defect in Ar + implanted samples was stable up to 1600 °C. It is suggested that the annealing behavior of Z1/Z2 depends on the source of its formation.

Electronic Transport Properties in Top-Gated Epitaxial Graphene on Silicon Carbide with ALD Al2O3 High-K Dielectric

Graphene Hall-bar devices, with aluminum oxide (Al2O3) high-k top gate, have been manufactured from epitaxial graphene grown in an Epigress VP508 hot-wall chemical vapor deposition reactor. Fully oxidized Al and Ti seeding layers were used for ALD growth of the Al2O3 gate dielectric. Carrier mobilities and densities were measured at temperatures ranging from 1K to 80K. Carrier mobility and density was also characterized for one device from 1K up to room temperature.