Tian Shen

Top-gated graphene field-effect-transistors formed by decomposition of SiC

Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions’ unique transport properties in graphene layers. The measured electron and hole mobilities on these fabricated graphene FETs are as high as 5400 and 4400cm2∕Vs, respectively, which are much larger than the corresponding values from conventional SiC or silicon.

Atomic-layer-deposited nanostructures for graphene-based nanoelectronics

Graphene is a hexagonally bonded sheet of carbon atoms that exhibits superior transport properties with a velocity of 108cm∕s and a room-temperature mobility of >15000cm2∕Vs. How to grow gate dielectrics on graphene with low defect states is a challenge for graphene-based nanoelectronics. Here, we present the growth behavior of Al2O3 and HfO2 films on highly ordered pyrolytic graphite (HOPG) by atomic layer deposition (ALD). To our surprise, large numbers of Al2O3 and HfO2 nanoribbons, with dimensions of 5–200nm in width and >50μm in length, are observed on HOPG surfaces at growth temperature between 200 and 250°C. This is due to the large numbers of step edges of graphene on HOPG surfaces, which serve as nucleation sites for the ALD process. These Al2O3 and HfO2 nanoribbons can be used as hard masks to generate graphene nanoribbons or as top-gate dielectrics for graphene devices. This methodology could be extended to synthesize insulating, semiconducting, and metallic nanostructures and their combinations.

Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3 dielectrics

Enhancement-mode (E-mode) n-channel InP metal-oxide-semiconductor field-effect transistors (MOSFETs) with 0.75–40μm gate length fabricated on a semi-insulating substrate with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors. A 0.75μm gate length E-mode n-channel MOSFET with an Al2O3 gate oxide thickness of 30nm shows a gate leakage current less than 10μA∕mm at the highest gate bias of 8V, a maximum drain current of 70mA∕mm, and a transconductance of 10mS∕mm. The peak effective mobility is ∼650cm2∕Vs and the interface trap density of Al2O3∕InP is estimated to be ∼(2–3)×1012∕cm2eV.

Determination of graphene work function and graphene-insulator-semiconductor band alignment by internal photoemission spectroscopy

We determined the band alignment of a graphene-insulator-semiconductor structure using internal photoemission spectroscopy. From the flatband voltage and Dirac voltage, we infer a 4.6×xa01011cm−2 negative extrinsic charge present on the graphene surface. Also, we extract the graphene work function to be 4.56u2009eV, in excellent agreement with theoretical and experimental values in literature. Electron and hole injection from heavily doped p-type silicon (Si) are both observed. The barrier height from the top of the valence band of Si to the bottom of the conduction band of silicon dioxide (SiO2) is found to be 4.3u2009eV. The small optical absorption in graphene makes it a good transparent contact to enable the direct observation of hole injection from Si to graphene. The barrier height for holes escaping from the bottom of Si conduction band to the top of SiO2 valence band is found to be 4.6u2009eV.

Observation of quantum-Hall effect in gated epitaxial graphene grown on SiC (0001)

Epitaxial graphene films examined were formed on the Si-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. A high-k gate stack on the epitaxial graphene was realized by inserting a fully oxidized nanometer thin aluminum film as a seeding layer, followed by an atomic-layer deposition process. The electrical properties of epitaxial graphene films are retained after gate stack formation without significant degradation. At low temperatures, the quantum-Hall effect in Hall resistance is observed along with pronounced Shubnikov–de Haas oscillations in diagonal magnetoresistance of gated epitaxial graphene on SiC (0001).

Ultraviolet/ozone treatment to reduce metal-graphene contact resistance

We report reduced contact resistance of single-layer graphene devices by using ultraviolet ozone treatment to modify the metal/graphene contact interface. The devices were fabricated from mechanically transferred, chemical vapor deposition grown single layer graphene. Ultraviolet ozone treatment of graphene in the contact regions as defined by photolithography and prior to metal deposition was found to reduce interface contamination originating from incomplete removal of poly(methyl-methacrylate) and photoresist. Our control experiment shows that exposure times up to 10u2009min did not introduce significant disorder in the graphene as characterized by Raman spectroscopy. By using the described approach, contact resistance of less than 200u2009Ωu2009μm was achieved for 25u2009min ultraviolet ozone treatment, while not significantly altering the electrical properties of the graphene channel region of devices.

First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching

The first well-behaved inversion-mode InGaAs FinFET with gate length down to 100 nm with ALD Al2O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. In contrast to the severe short-channel effect (SCE) of the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved S.S., DIBL and VT roll-off and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure design. The more accurate Dit estimation from the S.S. is also presented.

Interface studies of GaAs metal-oxide-semiconductor structures using atomic-layer-deposited HfO2∕Al2O3 nanolaminate gate dielectric

A systematic capacitance-voltage study has been performed on GaAs metal-oxide-semiconductor (MOS) structures with atomic-layer-deposited HfO2∕Al2O3 nanolaminates as gate dielectrics. A HfO2∕Al2O3 nanolaminate gate dielectric improves the GaAs MOS characteristics such as dielectric constant, breakdown voltage, and frequency dispersion. A possible origin for the widely observed larger frequency dispersion on n-type GaAs than p-type GaAs is discussed. Further experiments show that the observed hysteresis is mainly from the mobile changes and traps induced by HfO2 in bulk oxide instead of those at oxide/GaAs interface.

Magnetoconductance oscillations in graphene antidot arrays

Epitaxial graphene films have been formed on the C-face of semi-insulating 4H-SiC substrates by a high temperature sublimation process. Nanoscale square antidot arrays have been fabricated on these graphene films. At low temperatures, magnetoconductance in these films exhibits pronounced Aharonov–Bohm oscillations with the period corresponding to magnetic flux quanta added to the area of a single antidot. At low fields, weak localization is observed and its visibility is enhanced by intervalley scattering on antidot edges. At high fields, we observe two distinctive minima in magnetoconductance, which can be attributed to commensurability oscillations between classical cyclotron orbits and antidot array. All mesoscopic features, surviving up to 70K, reveal the unique electronic properties of graphene.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA∕mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3–5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ∼3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2∕Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge’s constant measured by low frequency noise spectral density characterization is 3.7×10−5 for the same device.