M.A. Melendes

AlInAs-GaInAs HEMTs utilizing low-temperature AlInAs buffers grown by MBE

Low-temperature AlInAs buffer layers incorporated in AlInAs-GaInAs HEMT epitaxial layers grown by MBE are discussed. A growth temperature of 150 degrees C followed by a short anneal is shown to eliminate kinks in the device I-V characteristic and sidegating and to reduce the output conductance dramatically.<<ETX>>

High-power V-band AlInAs/GaInAs on InP HEMTs

The DC and RF performance of delta -doped channel AlInAs/GaInAs on InP power high-electron-mobility transistors (HEMTs) are reported. A 450- mu m-wide device with a gate-length of 0.22 mu m has achieved an output power of 150 mW (at the 1-dB gain compression point) with power-added efficiency of 20% at 57 GHz. The device has a saturated output power of 200 mW with power-added efficiency of 17%. This is the highest output power measured from a single InP-based HEMT at this frequency, and demonstrates the feasibility of these HEMTs for high-power applications in addition to low-noise applications at V-band.<<ETX>>

High power and high efficiency AlInAs/GaInAs on InP HEMTs

The authors report on the development of AlInAs/GaInAs-on-InP power HEMTs (high electron mobility transistors). Output power densities of more than 730 mW/mm and 960 mW/mm with power-added efficiencies (PAE) of 50% and 40% respectively, were achieved at 12 GHz. When biased for maximum efficiency, a PAE of 59% and an output power of 470 mW/mm with 11.3 dB gain were obtained. These results demonstrate the viability of these HEMTs for power amplification. Considering that these HEMTs have an f/sub max/ of over 200 GHz, they should also have good power performance at millimeter-wave frequencies.<<ETX>>

Vertical scaling of ultra-high-speed AlInAs-GaInAs HEMTs

The scaling of the vertical dimensions of 0.15- mu m-gate-length Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As high-electron-mobility transistors (HEMTs) to reduce their well-known excessive gate leakage current, premature breakdown voltage, and poor output conductance is discussed. It is found that, with a proper choice of doping densities and layer thicknesses, it is possible to realize very-high-performance AlInAs-GaInAs HEMTs (f/sub T/=160 GHz, f/sub max/=300 GHz for 0.15- mu m*50- mu m devices) with low gate leakage current, high breakdown voltage (7.0 V), and very low DC output conductance (45-mS/mm). The DC output conductance exhibits a very strong dependence on the AlInAs doping-thickness product and appears to be a limiting factor in the device power gain. By reducing the doping-thickness product, it was possible to reduce the output conductance by a factor of 3 and thus increase the power gain cutoff frequency by a factor of 1.7.<<ETX>>

20-GHz high-efficiency AlInAs-GaInAs on InP power HEMT

A single-stage 20-GHz power amplifier was developed using a double-doped AlInAs-GaInAs-on-InP HEMT. Output power of 516 mW (0.645 W/mm) with power-added efficiency of 47.1% and 7.1-dB gain were obtained from an 800- mu m-wide device. The device had a saturated output power of more than 560 mW (0.7 W/mm). This is believed to be the highest combination of output power, power density, gain, and power-added efficiency reported for an InP-based FET at this frequency.<<ETX>>

Impact of buffer layer design on the performance of AlInAs-GaInAs HEMTs

Summary form only given. The authors report a study of the impact of buffer layer design on the characteristics of Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As HEMTs (high-electron-mobility transistors). The aim of the study is to understand and correct the problem of high output conductance observed in devices with a high transconductance. Devices with 1.0- mu m gate lengths were fabricated using modulation-doped Al/sub 0.48/In/sub 0.52/As-Ga/sub 0.47/In/sub 0.53/As epitaxial layers which had sheet charge densities between 3*10/sup 12/ and 3.5*10/sup 12/ cm/sup -2/ and mobilities at 300 K between 9000 and 10000 cm V/sup -1/ S/sup -1/. The different buffer layer designs used were: (1) a standard undoped Al/sub 0.48/In/sub 0.52/As buffer 250-nm-thick; (2) an Al/sub 0.48/In/sub 0.52/As buffer with a 20-AA thick highly doped p-type region 50 AA below the channel; (3) a Ga/sub 0.47/In/sub 0.53/As buffer with a 20-AA-thick highly doped p-type region below the channel; and (4) a low-temperature AlInAs buffer layer. The device with the low-temperature AlInAs had the best output characteristics, signifying that it was the best mode of confining electrons in the channel. >

Micromachining in III–V semiconductors using wet photoelectrochemical etching

Wet photoelectrochemical etching has been used to create deeply etched structures in both GaAs and InP. It was observed that the conductive n+ substrates etched quite rapidly, while semi‐insulating substrates exhibited enhanced etching only when a metal mask patterned the substrate, providing a low resistance contact for electron removal. It was further found that vertical profiles were achievable at high laser intensities, while a crystallographic taper was achieved at lower intensities. Finally, the limitations to microstructure geometry was explored in terms of the dynamics of the photogenerated carriers.

Highly selective reactive ion etch process for InP-based device fabrication using methane/hydrogen/argon

The etch rates of GaInAs and AlInAs were characterized using a mixture of methane, hydrogen, and argon as a function of self‐bias voltage. Effectively infinite etch selectivity between GaInAs and AlInAs was found for voltages below 200 V. This highly selective etch process was applied to the gate recess of a high electron mobility transistor device, and preliminary device measurements were made.

Via hole formation in semi-insulating InP using wet photoelectrochemical etching

Laser-assisted wet photoelectrochemical etching has been used in conjunction with a metal mask to make via holes in semi-insulating InP. It was found that the incident laser intensity and applied bias can control the degree of sidewall taper in the via holes as well as the vertical and lateral etch rates. It was found that the etch rate is faster for smaller via hole dimensions due to the smaller anode-to-cathode path length. There are however geometric limitations to the overall etched depth for small vias etched at low intensities due to the taper of the sidewalls. This method has demonstrated high etch rates and minimal undercut. Custom tailoring of the etch profile is achievable through adjustment of the etch parameters.<<ETX>>

InP-based HEMTs with AlIn/sub 1-x/P Schottky barrier layers grown by gas-source MBE

We report on the performance of a new class of InP-based HEMTs in which the conventional Al/sub x/In/sub 1-x/As Schottky barrier layer is replaced with Al/sub x/In/sub 1-x/P. The study of alternative Schottky barrier designs is aimed at improving the performance of InP-based HEMTs for applications that require high breakdown voltages, such as microwave power amplifiers. The typical low gate-to-drain breakdown voltage (BV/sub gd/) of <-5 V reported for Al/sub 0.48/In/sub 0.52/As/GaInPLs HEMTs limits the device performance for high power applications. A significant research effort has concentrated on improving BV/sub gd/ by increasing the aluminum concentration in the AlInAs layer. An increase in BV/sub gd/ from -5 V to -10 V has been achieved in our laboratory by increasing the aluminum concentration in the Al/sub x/In/sub 1-x/As Schottky layer from x=0.48 to x=0.70. Other researchers have reported BV/sub gd/ as high as -13 V for an In/sub 0.4/Al/sub 0.6/As/n+-InGaAs HFET with a gate length of 1.9 /spl mu/m. These breakdown voltages are, however, still much lower than typical values of BV/sub gd/>20 V reported for GaAs MESFETs and HEMTs. In addition, the increased Al concentration may limit both device reliability and yield due to poor gate metal adhesion to the Al-rich layer. Phosphorous containing materials are an attractive candidate for a wide bandgap Schottky layer design with low aluminum content. A pseudomorphic GaAs-based HEMT with Al/sub 0.52/In/sub 0.48/P barrier layer has been reported with BV/sub gd/ of -17 V and -10 V for 1.0 and 0.1 /spl mu/m long gate devices, respectively. More recently, a pseudomorphic channel InP HEMT with an Al/sub 0.2/In/sub 0.8/P barrier was reported with a BV/sub gd/=-15 V for a gate length of 0.5 /spl mu/m. In this paper, we present for the first time the performance of a Al/sub x/In/sub 1-x/P/AlInAs/GaInAs HEMT in which the channel is lattice matched to the InP substrate. We compare the performance of this new device with an Al/sub 0.6/In/sub 0.4/As/Al/sub 0.48/In/sub 0.52/As/Ga/sub 0.47/In/sub 0./