M. Ancona

Structuring a distributed program: the XMDS approach

Abstract The paper describes a methodology for the structured description of a distributed program, and its implementation within XMDS, a programming environment for the development of multiprocessor applications. Such programs are composed by a set of concurrent processes, each one consisting of separately compilable modules. The method is compared with those of Ada and Modula-2; the implementation is compared with the approach followed in the design of another programming environment for multimicros.

Integrating library modules into Pascal programs

We present the results of our experience in introducing modularity into the programming language Pascal in order to aid the creation and use of library modules. Our system performs the symbolic linking of source language modules producing a single Pascal text ready for compilation; performing the link phase before compilation anticipates interface consistency checks, and suggests a possible improvement of program development systems. Our extension is implemented in a preprocessor which ensures a complete compatibility with any standard Pascal compiler. In this paper we examine the main features of some high‐level programming languages which support modularization and data abstraction and some experiences in introducing modularity into Pascal; on this basis we describe our choice in detail. The design and implementation details are discussed and some examples are presented.

A hypergraph-based hierarchical data structure and its applications

Abstract A new data structure, which combines a hierarchical organization with a hypergraph-based representation, is presented. This structure, called a structured hypergraph, is a hierarchy of hypergraphs and combines the two concepts of modular decomposition and of description of an entity at different levels of abstraction. Two basic transformations, called refinement and abstraction, are described. These latter are the basic tools for defining and modifying a structured hypergraph. Applications of this structure as a hardware system model, as a description of the symbol table of modular language, as a hierarchical representation of solid objects, and as a model of computer networks are discussed.

Computational algorithms for hierarchically structured project networks

A new approach to large size network management based on a structured network representation is proposed. Definitions of arc-structured and vertex-structured networks are given and an extension of topological sorting and time computation algorithms is described. A generalization of the concept of vertex-structured networks is discussed.

Two language levels for system programming

Abstract An approach to system programming in High Level Language (HLL) based on the use of two language levels, named system and user level respectively, is presented. The user level language is interfaced to the system level in a protected and efficient way be means of the supervisor and user execution modes and trap system of the underlying hardware. This approach allows the system software development in two (or more) protected layers and makes easier the support of concurrent programming languages in distributed and multiprocessor embedded systems. This approach improves the efficiency of the use of an HLL, and makes it complete, in the sense that the system level language does not require a run-time support. All machine dependencies are solved by the compiler of the system level and a high level of abstraction and machine independence can be ensured both for the user and system levels of the language. Both levels of a language can be implemented by a single compiler, with few extensions due to the translation of some new constructs added to the system level.

Using structured steiner trees for hierarchical global routing

The Steiner problem in a hierarchical graph model, the structured graph, is defined. The problem finds applications to hierarchical global routing. Properties of minimum-cost Steiner trees in structured graphs are investigated. A “top-down” approximate solution to the Steiner problem in structured graphs, called a top-down Steiner tree, is defined, and an algorithm is given to compute such solution. The top-down Steiner tree provides also an approximate solution to the Steiner problem in graphs admitting a structured representation. The properties of such solution are discussed and some experimental results on the quality of the approximation are presented. A reduction in time complexity is demonstrated with respect to both exact and heuristic algorithms applied to such graphs.

Structured Graph Models: An Efficient Tool for VLSI Desgin

Hierarchical graph models are a powerful tool for describing VLSI circuits. They combine the representation of a hierarchical decomposition of a circuit with a graph description of its topological structure in terms of components and connections. Structured Graphs are an example of such models. In this paper we consider the graph-theoretic problems of spanning trees and Steiner trees in structured graphs. These have connections with the global routing problems in VLSI circuits.

The SPH-graph: a model to support VLSI design

A hierarchical graph-based model, called a structured hypergraph with ports (SPH-graph), is presented, that provides a structural description of VLSI objects at different levels of abstraction. The relationship between hardware description languages and the SPH-graph model are investigated by considering the VHSIC hardware description language (VHDL). It is shown, through an example, how a structural VHDL description of a hardware entity can be mapped on the model by using a basic set of primitives for SPH-graph manipulation.<<ETX>>

A hardware description language based on a hierarchical graph model

Abstract A model for the heirarchical structural description of hardware systems is proposed. This model, called SPH-graph, combines a tree describing the different levels of abstraction with a graph representation of the structure of the internal object components at any fixed level of specification. A language for structural hardware description is defined, to illustrate how descriptions of design objects can be mapped onto SPH-graphs.

32-Bit microprocessor architectures and extended abstract machines for high level languages

Abstract We analyze 32-bit microprocessor architectures with respect to the support they provide for high level languages. These architectures are compared with the P-code abstract machine which is used in many Pascal implementations. The comparisons shows that P-code and other abstract machines are of lower level with respect to 32-bit microprocessors. The design principles of an extended intermediate abstract machine, which exploits the features provided by 32-bit microprocessors in supporting high level languages and still maintains target independence, are outlined. The support provided by different architectures to modular software development is considered. We remark how specific architectural features simplify the linking algorithm.