M.B. Barron

New monolithic high-speed analog delay lines

Bucket-brigade circuit implementation with junction or metal-silicon field-effect switching elements provides good low- and high-frequency performance at low clocking voltages with high packing density, simple processing, and good stability.

Application of JFET-Mesfet devices to bucket-brigade circuits

Electronically-controlled delay lines based on the bucket-brigade concept have been made in the past by using MOSFET and bipolar structures. To the present time, depletion mode JFET or MESFET structures have not been used for such circuits. In this paper, the operating characteristics of JFET devices are discussed with reference to their use in a bucket brigade delay line, and it is shown that by using JFET or MESFET switches a significant improvement in performance can be expected from such circuits. The high frequency performance of a bucket brigade circuit is to a large extent governed by the current flow capability of the switching devices. For a MOSFET this is given by: I_{DS} \frac{dQ}{dt} = \frac{g_{m}}{2} (V_{gs} = Vth) for a JFET we have: I_{DSS} = \frac{dQ}{dt} = \frac{g_{m}}{2} V_{p} (1- \frac{V_{gs}}{V_{p}})^{2} The bandwidth of these devices is therefore directly related to the value of g m , which in a p-channel MOSFET device is of the order of 24 µmhos/ square and for a JFET structure of the order of 150 µmhos/square. It follows, therefore, that data rates far in excess of those already reported for MOSFET Brigades (5 - 10 MHz) can be expected from JFET structures. For low frequency operation, the bipolar brigade is severely handicapped by relatively high leakage currents which are primarily due to the enlarged base area required for the storage capacitor. With JFET brigades (using MOS capacitors) the leakage currents are considerably reduced. A ten stage JFET brigade has been operated successfully at 100°C at a clocking frequency of 100 Hz, and at 10 MHz with a 2 volt clock.

Improved Schottky clamped (T/sup 2/L) circuits

Al-Si Schottky clamped transistors used as fast switching signal devices or in integrated circuits are superior to gold-doped transistors for such parameters as low-level current gain, leakage current I/SUB CO/, and propagation delay t/SUB pd/. A digital application is used to show how some of these parameters can be optimized for a T/SUP 2/L circuit, providing high switching speed (t/SUB pd/ 4 to 5 ns) and a 40-percent better worst-case low-level noise margin than the usual gold-doped T/SUP 2/L circuit.