M. Bartek

Vacuum sealing of microcavities using metal evaporation

Abstract A new encapsulation technique to seal a vacuum-tube microcavity hermetically at low pressures, based on aluminium evaporation, is presented and its performance is compared to conventional low-pressure chemical vapour deposition (LPCVD) reactive sealing. The microdiode consists of an in-cavity recessed single-crystalline silicon cathode tip above which a polycrystalline silicon anode is suspended on a silicon-rich nitride layer. The diode cavity is cleared from the sacrificial oxide in buffered HF through the horizontal etch-access channels between the polysilicon anode and the silicon-rich nitride isolation layer. Vacuum sealing of the cavity using LPCVD polycrystalline silicon results in polysilicon deposits ( > 50 nm) inside the cavity, and thus in a non-acceptable degradation of the cathode-tip curvature. When sealing is performed using aluminium evaporation, no deposits inside the cavity are observed and pressures below 10 Pa can be expected. Applications of the technique presented are not restricted to micro vacuum diodes, but also include various type of hermetically sealed micromechanical structures, where deposits inside the sealed cavity are undesirable.

Design and fabrication of on-chip integrated polySiGe and polySi Peltier devices

Abstract On-chip integration of Peltier devices introduces a number of new fabrication considerations and yields a device with increasingly complex operating characteristics, when compared to the discrete device. Due to fabrication compatibility, polycrystalline SiGe (polySiGe) and polycrystalline Si (polySi) are the thermoelectric materials of choice. Device performance is compared for different thermoelectric materials, and the impact of the non-idealities on performance is analysed, interpreting the results in a graphical manner. The primary conclusion from this study is that, although often ignored, the contact resistance of the device is the most prominent non-ideality. Using a fully compatible process, various Peltier devices have been fabricated. The initial values from the measurements performed on both polySi and polySiGe correspond well to those found in literature, validating the design concept, although further optimisation is required.

A CMOS optical microspectrometer with light-to-frequency converter, bus interface, and stray-light compensation

A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry-Perot (F-P) etalons (each one with different resonance cavity length), photodetectors, and circuits for readout, multiplexing, and driving a serial bus interface has been fabricated in a standard 1.6-/spl mu/m CMOS technology (chip area 3.9 /spl times/ 4.2 mm/sup 2/). The result is a chip that can operate using only four external connections (including V/sub dd/ and V/sub ss/) covering the optical range of 380-500 nm with FNVHM = 18 nm. Frequency output and serial bus interface allow easy multisensor, multichip interfacing using a microcontroller or a personal computer. Also, stray-light compensation techniques are implemented. Power consumption is 1250 /spl mu/W at a clock frequency of 1 MHz.

A general purpose reconfigurable MEMS-based attenuator for Radio Frequency and microwave applications

In this paper we present a power attenuator for RF (RadioFrequency) and microwave signals entirely designed in MEMS (MicroElectroMechanical-System) technology. It is fabricated in the RF-MEMS technology available at Fondazione Bruno Kessler (FBK) based on a surface micromachining process. The network is realized in a low-cost manufacturing process and its dimensions are significantly compact compared to traditional implementations of RF power attenuators. More interestingly, employment of MEMS technology for such architecture enables a very large reconfigurability, making the network compatible with different standards and usable in several wireless communication systems. Electromechanical and RF behaviour of the discussed network are simulated and compared against experimental results collected by the first fabricated samples. RF measured performances are rather promising in spite a technology issue occurred during the fabrication deteriorating the attenuator low-frequency characteristic. RF modelling of such issue (already fixed in the batches being currently fabricated) is shown and discussed through this paper.

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 /spl mu/m to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to single-crystalline silicon.

Bipolar-compatible epitaxial poly for smart sensors: stress minimization and applications

Abstract This paper presents the optimization of the fabrication process for bipolar-compatible epipoly for micromachining applications. The use of an epitaxial reactor to grow polysilicon enables the growth of monocrystalline silicon (for bipolar electronics) and polysilicon on top of oxkle (for MEMS) in a single deposition step. However, after bipolar processing the early structures showed compressive strain in the epipoly layer, which then required careful MEMS design. The cause of this compressive strain is shown to be the oxidation steps in the bipolar process. The occurrence of this strain can be explained by the presence of oxygen in the epipoly. An alternative processing technique, where the epipoly is doped using implantation and shielded from oxidation by a nitride layer during further bipolar processing, yields epipoly layers without compressive strain. The full thermal budget of the bipolar process is used to diffuse and activate the implanted epipoly dopant. Functional thermal and electrostatic sensor and actuator structures have been fabricated to demonstrate the feasibility of this process

Integrated 5.7 GH size antenna for wireless sensor networks

We report on design, fabrication and characterization of chip-size antennas for operation at 5.7 GHz and use in wireless sensor networks. Application of wafer-level chip-scale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna types (patch and folded patch) allows on-chip integration and is the main novelty of our work. A short-range wireless link between two systems both equipped with an 8/spl times/8 mm/sup 2/ patch antenna (measured characteristics: 5.705 GHz central frequency, 90 MHz bandwidth @ -10 dB, 0.3 dB gain, 18 % efficiency) realized on a high-resistivity silicon (HRS) substrate is demonstrated. A folded-patch antenna built on two stacked glass substrates allows size reduction down to 4.5/spl times/4/spl times/1 mm/sup 3/ and has a projected efficiency of 60%.

Comparison of via-fabrication techniques for through-wafer electrical interconnect applications

Several techniques for fabrication of through-wafer vias in silicon have been compared in terms of achievable via diameter, shape and geometry and their influence on mechanical strength of silicon dies/wafers. The assessed techniques are: powder blasting, laser melt cutting, laser ablation, and deep reactive ion etching. The resolution of each method and influence on geometry was evaluated by fabrication of through-wafer holes and slots in 240 /spl mu/m-thick silicon wafers. The mechanical strength is measured using ring-on-ring (RoR) and four-point bending methods. Additional stress-relief post-processing was applied to improve mechanical strength. Comparing the performance of bipolar transistors, before and after fabrication of laser ablated vias, indicates that the electrically affected zone does not exceed 10-20 /spl mu/m around the via edge.

A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface

A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry-Perot etalons (each one with a different resonance cavity length), photodetectors, and circuits for readout, multiplexing, and driving a serial bus interface has been fabricated in a standard 1.6 /spl mu/m CMOS technology (chip area 3.9 /spl times/ 4.2 mm/sup 2/). The result is a chip that can operate using only four external connections (including V/sub dd/ and V/sub ss/) covering the optical range of 380-500 nm with full-width half-maximum (FWHM) = 18 nm. Frequency output and serial bus interface allow easy multisensor and multichip interfacing using a microcontroller or a personal computer. Power consumption is 1250 /spl mu/W for a clock frequency of 1 MHz.

An integrated silicon colour sensor using selective epitaxial growth

Abstract An integrated silicon colour sensor using selective epitaxial growth (SEG) of silicon is presented. The sensor concept is based on the strong wavelength dependence of the photon absorption coefficient in silicon in the visible spectral range. Photocurrents of three vertically stacked photodiodes, with the desired position and thickness of the depletion regions, represent full tricolorimetric information. The upper two photodiodes are integrated in the 1.2 μ thick SEG silicon, which is grown on the conventional epilayer where the lower photodiode is placed. High-quality SEG silicon with pattern-insensitive growth has been achieved. Diodes formed in SEG silicon show an ideality factor close to 1, provided the edges are oriented in the [100] directions. The first prototypes of the colour sensor have been fabricated, and measured spectral responses give reasonable agreement with simulation. Using the SEG process together with low-temperature deposited masking oxide (TEOS), maintains compatibility with standard bipolar processing and enables the integration of read-out circuitry to realize a truly smart sensor.