A. Polyakov

Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 /spl mu/m to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to single-crystalline silicon.

Substrate options and add-on process modules for monolithic RF silicon technology

Add-on process modules as enhancements of standard high-frequency silicon integration processes are discussed. Such modules can be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. High-resistivity silicon substrates, the patterned metal ground shield, and bulk micromachining are presented as examples in each category, respectively.

Integrated 5.7 GH size antenna for wireless sensor networks

We report on design, fabrication and characterization of chip-size antennas for operation at 5.7 GHz and use in wireless sensor networks. Application of wafer-level chip-scale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna types (patch and folded patch) allows on-chip integration and is the main novelty of our work. A short-range wireless link between two systems both equipped with an 8/spl times/8 mm/sup 2/ patch antenna (measured characteristics: 5.705 GHz central frequency, 90 MHz bandwidth @ -10 dB, 0.3 dB gain, 18 % efficiency) realized on a high-resistivity silicon (HRS) substrate is demonstrated. A folded-patch antenna built on two stacked glass substrates allows size reduction down to 4.5/spl times/4/spl times/1 mm/sup 3/ and has a projected efficiency of 60%.

Comparison of via-fabrication techniques for through-wafer electrical interconnect applications

Several techniques for fabrication of through-wafer vias in silicon have been compared in terms of achievable via diameter, shape and geometry and their influence on mechanical strength of silicon dies/wafers. The assessed techniques are: powder blasting, laser melt cutting, laser ablation, and deep reactive ion etching. The resolution of each method and influence on geometry was evaluated by fabrication of through-wafer holes and slots in 240 /spl mu/m-thick silicon wafers. The mechanical strength is measured using ring-on-ring (RoR) and four-point bending methods. Additional stress-relief post-processing was applied to improve mechanical strength. Comparing the performance of bipolar transistors, before and after fabrication of laser ablated vias, indicates that the electrically affected zone does not exceed 10-20 /spl mu/m around the via edge.

Design of a folded-patch chip-size antenna for short-range communications

We report on design of an integrated folded shorted-patch (FSP) chip-size antenna for operation at 5.7 GHz and use in short-range wireless communications. Application of wafer-level chip-scale packaging (WLCSP) techniques like adhesive wafer bonding and through-wafer electrical via formation, combined with the selected antenna type allows antenna on-chip integration. The operating characteristics of a folded S-P antenna built on two stacked glass substrates were analysed with respect to substrate thickness, middle patch length and substrate sidewall angles. Antenna size reduction down to 4x4x1 mm3, efficiency of 66 % and bandwidth of 62 MHz are predicted.

Circuit partitioning and RF isolation by through-substrate trenches

In this work, theoretical and experimental analysis of RF crosstalk suppression by substrate thinning and trenching is performed. Medici (2D solver) simulation results show that high isolation can be achieved by using high resistivity thinned substrate and through-substrate trenches. Measurements on dedicated G-S-G test structures implemented on thinned Si substrates (thickness 20-100 /spl mu/m) with and without through-substrate trenches (trench width 5-100 /spl mu/m) show that isolation between two single-ended capacitive substrate contacts can effectively be controlled by these trenches. While the partial trenches provide additional isolation of /spl sim/10 dB at 1 GHz, the full trenches (forming isolated silicon islands) provide additional isolation of /spl sim/30 dB at 1 GHz.

Through-substrate trenches for RF isolation in wafer-level chip-scale package

The wafer-level chip-scale packaging (WLCSP) concept offers a lot of new possibilities. Not only is the package size smaller, but also features to improve the performance can be easily realized. It is widely known that the radio frequency integrated circuit (RFIC) suffers from substrate coupling due to its electrically conducting substrate. The downscaling of RFIC and the increasing operating frequency make the substrate coupling even more problematic. This paper proposes through-substrate trench as schemes to suppress the substrate coupling. A through-substrate trench can easily be realized using WLCSP concept without any drawback in mechanical reliability. Topologies for equivalent circuit modeling approach are also introduced in this work.

Wafer-level chip-scale packaging for low-end RF products

The paper gives a short overview of wafer-level chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of RF passives (inductors, antennas) are addressed. The Shellcase-type wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.

Mechanical stability and handling-induced failure of micromachined wafers for RF applications

Micromachining has been identified as the enabling technology for future RF silicon ICs (Katchi et al, 2001). In this paper, a study of mechanical stability and handling-induced mechanical failure of micromachined RF silicon wafers, considering excessive bending and fracture as the primary failure modes, is presented. Selected mechanical characteristics of [100]-silicon wafers, with arrays of rectangular recesses and circular through-wafer vias, have been determined theoretically using FEM simulations and experimentally by performing 3- and 4-point bending measurements. Recommendations for layout and geometry of the micromachined structures are derived. It is shown that selective substrate removal by forming recesses on up to 40% of the initial surface area has only a moderate influence on the wafer stiffness and therefore processing using conventional equipment is not jeopardized. The handling-related reliability can be improved by minimizing the maximum stress levels within the micromachined wafers. This can be achieved by minimizing the characteristic recess dimensions, maximizing the separations between them, and smoothing of any sharp features like rough surfaces, edges and corners.

An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP), Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of ≫ 150 μm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a -10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates.