M. D. Stewart

Fabrication and Electrical Characterization of Fully CMOS-Compatible Si Single-Electron Devices

We present electrical data of silicon single-electron devices fabricated with CMOS techniques and protocols. The easily tuned devices show clean Coulomb diamonds at T = 30mK and a charge offset drift of 0.01e over eight days. In addition, the devices exhibit robust transistor characteristics, including uniformity within about ±0.25 V in the threshold voltage, gate resistances greater than 10 GΩ, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a silicon-foundry-compatible process for single-electron device fabrication.

A quantitative study of bias triangles presented in chemical potential space

We present measurements of bias triangles in several biasing configurations. Using a capacitive model and two fit parameters we are able to predict the shapes and locations of the bias triangles in all measurement configurations. Furthermore, analysis of the data using this model allows us to present data from all four possible bias configurations on a single plot in chemical potential space. This presentation allows comparison between different biasing directions to be made in a clean and straightforward manner. Our analysis and presentation will prove useful in demonstrations of Pauli-spin blockade where comparisons between different biasing directions are paramount. The long term stability of the CMOS compatible Si/SiO2 only architecture leads to the success of this analysis. We also propose a simple variation to this analysis that will extend its use to systems lacking the long term stability of these devices.

AC signal characterization for optimization of a CMOS single-electron pump

Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

Effect of device design on charge offset drift in Si/SiO2 single electron devices

We have measured the low-frequency time instability known as charge offset drift of Si/SiO2 single electron devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance Cm between defects and the quantum dot, and increase in the total defect capacitance Cd due to the top gate. These results depart from the prominent interpretation that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of devices is a challenge.