M. Gall

Statistical analysis of early failures in electromigration

The detection of early failures in electromigration (EM) and the complicated statistical nature of this important reliability phenomenon have been difficult issues to treat in the past. A satisfactory experimental approach for the detection and the statistical analysis of early failures has not yet been established. This is mainly due to the rare occurrence of early failures and difficulties in testing of large sample populations. Furthermore, experimental data on the EM behavior as a function of varying number of failure links are scarce. In this study, a technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone Bridge is presented. Three types of structures with a varying number of Ti/TiN/Al(Cu)/TiN-based interconnects were used, starting from a small unit of five lines in parallel. A serial arrangement of this unit enabled testing of interconnect arrays encompassing 480 possible failure links. In addition, a Wheatstone Bridge-type wiring using four large arrays in each...

Electromigration early failure distribution in submicron interconnects

The early failure issue in electromigration (EM) has been an unresolved subject of study over the last several decades. A satisfying experimental approach for the detection and analysis of early failures has not yet been established. In this study, a new technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone bridge is presented. A total of more than 20,000 interconnects were tested. The results indicate that the EM failure mechanism studied here follows log-normal behaviour down to the 4 sigma level.

Detection and analysis of early failures in electromigration

The early failure issue in electromigration (EM) has been an unresolved subject of study over the last several decades. A satisfying experimental approach for the detection and analysis of early failures has not been established yet. In this study, a technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone Bridge is presented. A total of more than 20u2009000 interconnects were tested. The results indicate that the EM failure mechanism studied here follows lognormal behavior down to the four sigma level.

Electromigration failure model : its application to W plug and Al-filled vias

Abstract For Al–Cu VLSI interconnects at tungsten (W) plug contact/via areas, a new electromigration (EM) failure model has been established. A series of experiments was performed to verify the proposed model using novel test structures. This paper discusses the lifetime extrapolations using the model and experimental data which predicts that lifetimes of Al–Cu interconnects at use conditions are dominated by Cu drift, or incubation times. This paper also discusses EM experimental results obtained for the Al-filled via which is a promising candidate for replacing W plug vias due to requirements of process simplification and cost reduction in multilevel metallizations. EM failure distributions from Al-filled vias show large standard deviations. This observation is explained through extensive failure analysis of EM-failed specimens. The application of the established EM model to Al-filled vias is discussed.

Statistical evaluation of device-level electromigration reliability

A new test structure for electromigration failure analysis of via-interconnect metallization schemes was developed. The new ensemble of via-interconnect structures can be wire-bonded within the test chip using different configurations thus selecting the number of vias under test. The correlation of the experimental data for different numbers of vias with the results of numerical simulation allows a better insight on the statistical properties of the failure mechanism. The new testing procedure allows extrapolation to operating conditions at the device level with tighter confidence intervals. Furthermore, critical length effects were investigated using many-via chain test structures with different interconnect lengths in drift-velocity type experiments. At interconnect lengths close to the critical Blech-length, resistance saturation effects were encountered and used for calculations of the critical current⋅length product, (jl)*.

Dependence of EM performance on linewidth for Cu dual-inlaid structures

EM is a diffusion phenomenon under the influence of driving forces. The major diffusion paths for Cu dual inlaid structures are believed to be interfaces and grain boundaries. Cu dual inlaid structures usually have a refractory metal barrier layer and are capped with a dielectric layer. The fastest diffusion path in such a structure is believed to be the Cu-dielectric interface. We studied the relationship between EM behavior and metal line- width for two types of EM test structures. It was found that the median time to failure (MTTF) increased significantly as the metal line-width increased for each type of structures when tested under the same current density. In one case, the MTTF increased by 200 percent as the metal line-width was doubled. Microstructure analysis on the metal lines showed that the wider lines had almost a bamboo structure while the narrower lines consisted of small grains. Therefore, the dramatic decrease in MTTF in the narrower line structure was most likely due to a significant increase in grain boundary diffusion. Mathematical treatment has been performed on the experimental data based on the assumption that the MTTF is reciprocally proportional to the drift velocity or the diffusivity, in this case, of Cu. It has been concluded that grain boundaries can be the fastest diffusion path in Cu dual inlaid structures when the grain size is small.

Thermal stresses in Cu damascene submicron line structures

Thermal stress in passivated blanket Cu and in passivated 0.2 μm wide damascene Cu lines have been characterized using x-ray diffraction and compared with that measured for 0.2 μm AlCu line structures. The microstructure plays an important role in controlling the thermal stress behavior, particularly for Cu due to its elastic anisotropy. Microstructural analysis of the blanket Cu revealed a strong (111) fiber texture. The damascene Cu lines had a strong (111) texture along with a weak in-plane (110) texture component that can be explained by surface energy considerations. The grain size of damascene Cu is constrained by the linewidth. The observed stress behavior of blanket Cu films shows stress hysteresis and plastic deformation. Under thermal cycling, the 0.2 μm wide Cu lines show a nearly hydrostatic triaxial stress state with linear elastic behavior. Compared with 0.2 μm wide AlCu lines, the principal stresses are generally lower in Cu lines and the difference can be attributed to the thermoelastic pr...

A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations

A comparison of via overetch is made between a conventional integration using aluminum interconnects plus tungsten via plugs and a dual-inlaid integration using copper. Excessive overetch for Al interconnects can cause reliability problems because of veil formation, as well as create very high aspect ratio recesses that are difficult to fill. The reasons for variation in interlevel dielectric (ILD) thickness and via etch rate are discussed. For the Al-W interconnect system, oxide CMP controls the ILD thickness. In addition, the via etch rate has been observed to drop over time. Both contribute significant variations to via overetch. For a via-first dual-inlaid integration, the ILD deposition determines the via depth uniformity. In metal-first dual-inlaid, the metal trench etch controls the via depth. In both cases, the via etch rate has been optimized to be more stable over time. Overall, the Al-W integration has a very wide range of via depths and etch rates that must be tolerated, whereas the dual-inlaid integrations have only a few percent of variation.

Comparison of via electromigration for Cu, CVD-Al, and CVD-W

For Al-Cu VLSI interconnects at tungsten (W) plug contact/via areas, a new electromigration (EM) failure model has been established. A series of experiments were performed to verify the proposed model using novel test structures. This paper discusses the lifetime extrapolation using the model and experimental data which predicts that lifetimes of Al-Cu interconnects at use conditions are dominated by Cu drift, or incubation times. This paper also discusses EM experiment results obtained for the Al filled via which is a promising candidate for replacing W plug vias due to requirements of process simplification and cost reduction in multilevel metallizations. EM failure distributions from the Al filled vias show large standard deviations. This observation is explained through extensive failure analysis of EM-failed specimens. For performance improvement in high-speed logic devices, Cu metallization schemes are being developed. An application of the established failure model to the different metallization sy...

Statistical Analysis of Electromigration in Cu Interconnects With Multi‐link Test Structures

The continual downward scaling of devices and increases in drive current have required an ever shrinking interconnect pitch and higher current densities. In order to overcome both the higher signal delay, as well as reliability concerns, new metallization technologies like Cu interconnects and low‐k interlevel dielectrics have been developed. The implementation of inlaid Cu interconnects introduces a new set of material systems and geometries which results in new mass transport and failure mechanisms under electromigration. This study focuses on the characterization and understanding of electromigration‐induced failures in advanced, 0.13 μm technology node Cu interconnects. Statistically based methodologies, using multi‐link test structures, were developed and used to further understand the reliability of these advanced interconnects. Single‐inlaid structures designed to test both the upper and lower interfaces associated with a Cu via were used to understand the role of void formation and interconnect ge...