M. H. Chang

Stress-Induced Positive Charge in Hf-Based Gate Dielectrics: Impact on Device Performance and a Framework for the Defect

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability Delta Vth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates Delta Vth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of Delta Vth is clarified.

An Analysis of the NBTI-Induced Threshold Voltage Shift Evaluated by Different Techniques

Negative bias temperature instability (NBTI) is limiting the lifetime of pMOSFETs, and it is often monitored by the shift of threshold voltage DeltaV_t. Different techniques have been developed to extract DeltaV_t, including the conventional extrapolation of the quasi-dc transfer characteristic <i>I</i> _d ~<i>V</i> _g and the more recent extrapolation of ultrafast pulse <i>I</i> _d ~<i>V</i> _g and the on-the-fly evaluation at stress bias. After the same stress, these techniques can produce a DeltaV_t difference of up to one order of magnitude. The interpretation of this large difference is still controversial. The objective of this paper is to bridge the gap between the DeltaV_t values extracted from these techniques. Degradation and recovery during measurement, measurement and truncation errors, and calculation of transconductance are all examined. After taking these factors into account, the gap in DeltaV_t still cannot be filled, and hence, the effect of sensing V_g on DeltaV_t must now be considered. It is found that | DeltaV_t | increases with sensing | V_g |, and therefore, the popular assumption of DeltaV_t being independent of sensing V_g is invalid. After taking both the effect of sensing V_g and recovery into account, the gap in |DeltaV_t| is successfully bridged. The difference between the effect of sensing V_g and recovery is explored, and the results show that they are two different phenomena. This paper provides test engineers a method for determining the worst case DeltaV_t under a given operation voltage.

Effects of Measurement Temperature on NBTI

Negative bias temperature instability (NBTI) is a pressing reliability issue for the CMOS industry. NBTI has been measured at stress temperature in most of the recent works. For the first time, this letter will demonstrate that, for a given number of defects, the threshold-voltage shift measured at stress temperature can be less than half of its value at room temperature. As a result, the data obtained at different measurement temperatures should not be used for extracting the thermal enhancement of defect creation. In the future, this newly identified dependence on measurement temperature should be taken into account when estimating the NBTI limited lifetime of pMOSFETs

On positive charge formed under negative bias temperature stress

As nitrogen concentration in silicon oxynitride (SiON) increases, negative bias temperature instability (NBTI) becomes a limiting factor for device lifetime. Despite recent efforts, there are confusions and issues remaining unsolved. One of them being how important positive charge formation in SiON is for NBTI and whether all positive charges are the same type. The objective of this work is to investigate positive charge formed in SiON during negative bias temperature stress (NBTS). In comparison with the positive charge formed during substrate hole injection where interface state generation is negligible, it will be shown that NBTS can induce three different types of positive charges: as-grown hole trapping, antineutralization positive charge (ANPC), and cyclic positive charge. Efforts have been made to search for the feature of NBTI, which cannot be explained without involving positive charge. It is unambiguously identified that the impact of measurement temperature on NBTI originates from only one type...

Assessment of capture cross sections and effective density of electron traps generated in silicon dioxides

Generation of acceptor-like electron traps in gate oxides is an important source for device instability. Despite previous efforts, capture cross sections are not unambiguously determined, and there is confusion on how many capture cross sections genuinely exist. Neither is the dependence of trap density for a given capture cross section on stress level clear. The objective of this paper is to fill this knowledge gap by investigating electron-trapping kinetics. There are a number of obstacles for such an investigation including the simultaneous occurrence of trapping and trap generation, stability of trapping, and effects of positive charges. Through careful selection of experimental conditions and testing samples, the authors have been able to overcome these obstacles. In particular, their recent work in this area has allowed them to develop a new method for correcting the effect of positive charges. After removing all uncertainties, the authors are able to identify a capture cross section as large as 10/sup -13/-10/sup -14/ cm/sup 2/ for the generated acceptorlike trap. It will be shown that electron trapping follows the first-order model, and there is also a smaller capture cross section in the region of 10/sup -15/-10/sup -16/ cm/sup 2/. To the best of their knowledge, for the first time, the authors will show that the density of the larger trap increases with stress, but the density of the smaller trap clearly saturates.

Dominant Layer for Stress-Induced Positive Charges in Hf-Based Gate Stacks

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The location of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiON/IL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, positive charges cannot be reduced by using a thinner HfSiON film.

Electrical signature of the defect associated with gate oxide breakdown

Oxide breakdown is an important issue for MOS devices. It is widely believed that defects generated within the oxides are responsible for the breakdown. However, it is still not clear which type of the various generated defects is the main cause for the failure. This paper unambiguously shows that generated hole traps, low-field electron traps, and high-field electron traps with a capture cross section of 10/sup -15/-10/sup -16/ cm/sup 2/ are not the main source of the breakdown. The generated high-field electron trap with a capture cross section in the order of 10/sup -14/ cm/sup 2/ is the only defect having all the characteristics required for breaking down the oxide. This paper should provide useful information for modeling oxide breakdown.

Process-induced positive charges in Hf-based gate stacks

Hf-based gate stacks will replace SiON as a gate dielectric even though our understanding of them is incomplete. For an unoptimized SiO2 layer, an exposure to H2 at a temperature over 450 °C can lead to positive charging. In this work, we will show that a thermal exposure of Hf-based gate stacks to H2 can also induce a large amount of positive charge (∼1013 cm−2). There is little information available on this process-induced positive charge (PIPC) and the objective of this work is to fill this knowledge gap. The work is divided into two parts: an investigation of the features and properties of PIPC, followed by an exploration of its dependence on process conditions. It will be shown that PIPC does not originate from the generation of interface states, is stable both thermally and electrically, and has a large sample-to-sample variation. It consists of two components: fixed and mobile. Regarding its dependence on process conditions, PIPC occurs in both HfO2 and Hf-silicate stacks, in devices with either Ta...

Impact of different defects on the kinetics of negative bias temperature instability of hafnium stacks

For SiO2 or SiON, negative bias temperature instability (NBTI) generally follows a power law. There is less information available for the NBTI of Hf stacks and it will be studied and compared with that of SiO2 in this work. We found that the power factor for Hf stacks was substantially smaller and the NBTI kinetics has a “flat-then-rise” feature. The flat region at short stress time originates from the preexisting cyclic positive charge in Hf stacks, which is different from the defect responsible for the rising part at longer time and leads to the smaller power factor for Hf stacks.

On the role of hydrogen in hole-induced electron trap creation

Generation of acceptor-like electron traps in gate oxide is an important source for the instability of MOS transistors. Agreements have not been reached on the dominant damaging species. When injected electrons were orders of magnitude higher than injected holes, it was proposed that hydrogen release and its subsequent transportation through the oxide dominated the generation. It was also reported that holes were more efficient in creating electron traps than electrons. However, the physical process for the hole-induced generation is not clear. This work is focused on one issue: is the release and subsequent transportation of hydrogenous species also important for hole-induced electron trap generation? Effects of hydrogenous species released near the two interfaces and in the bulk of oxides are examined. It is found that the release and subsequent transportation of hydrogenous species are not important for the hole-induced generation. Results support that holes can interact directly with the oxide to generate electron traps without going through hydrogen as intermediate species.