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Dive into the research topics where M.-H. Liao is active.

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Featured researches published by M.-H. Liao.


IEEE Transactions on Electron Devices | 2012

Erratum to “Additional Nitrogen Ion-Implantation Treatment in STI to Relax the Intrinsic Compressive Stress for n-MOSFETs”

M.-H. Liao; Chih Hua Chen; Li Cheng Chang; Chen Yang; Ssu Chieh Kao

Based on the stress extraction and measurement by the atomic-force-microscope-Raman technique with nanometer-level space resolution, the high compressive stress about 700 MPa on the Si critical dimension (CD) is observed in the current complementary metal-oxide-semiconductor (CMOS) transistor. The difference of thermal expansion between Si and Shallow trench isolation (STI) oxide during the total thermal budget for the standard CMOS transistor manufacture process results in this high compressive stress in Si CD and will further degrade the electron carrier mobility about 25% seriously. In order to relax this intrinsic-processed compressive stress in Si CD and recover this device performance loss, the novel process is proposed in this paper in addition to the usage of one-side pad-SiN layer demonstrated in our previous work. With this novel process of additional nitrogen-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress in the Si CD can be achieved by the smaller difference of thermal expansion coefficients between Si and highly n-doped SiO2 STI oxide. The formation of Si-N bonding in the STI-oxide region can be monitored by Fourier-transform infrared spectroscopy spectra, and the thermal expansion coefficients for Si, SiO2, and SiN are 2.6, 0.4, and 2.87 ppm/K, respectively. The relaxation of intrinsic-processed compressive stress in the Si CD of about 400 MPa by this proposed additional nitrogen IMP treatment contributes 14 % electron-carrier-mobility enhancement/recovery. The experimental electrical data agree well with the theoretical k.p calculation for the strained-Si theory.


IEEE Transactions on Electron Devices | 2017

Systematic Investigation of Self-Heating Effect on CMOS Logic Transistors From 20 to 5 nm Technology Nodes by Experimental Thermoelectric Measurements and Finite Element Modeling

M.-H. Liao; C.-P. Hsieh; Chang-Chun Lee

The characteristics of thermal conductivity (<inline-formula> <tex-math notation=LaTeX>


IEEE Transactions on Electron Devices | 2015

Erratum to “Additional Nitrogen Ion-Implantation Treatment in STI to Relax the Intrinsic Compressive Stress for n-MOSFETs” [Aug 12 2033-2036]

M.-H. Liao; Chih Hua Chen; Li Cheng Chang; Chih-Wei Yang; Ssu Chieh Kao

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IEEE Transactions on Electron Devices | 2013

Relaxation of Residual Stress in Bent GaN Film on Sapphire Substrate by Laser Treatment With an Optimized Surface Structure Design

Chih Hua Chen; M.-H. Liao; Li Cheng Chang; Ssu Chieh Kao; M.-Y. Yu; G.-H. Liu; Meng-Chi Huang

</tex-math></inline-formula>) with different operated temperatures (<inline-formula> <tex-math notation=LaTeX>


2012 International Silicon-Germanium Technology and Device Meeting (ISTDM) | 2012

The Optimization of SiGe Hetero-Structure Thin-Film Solar Cell by the Theoretical Calculation and Quantitative Analysis

M.-H. Liao; You-Yin Chen; Chung-Hui Chen; Li-Te Chang; Czau-Siung Yang; C.-F. Hsieh

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Procedia Engineering | 2014

Optimized Si0.5Ge0.5/Si Interface Quality by the Process of Low Energy Hydrogen Plasma Cleaning and Investigation by Positron Annihilation Spectroscopy☆

Cho-Fan Hsieh; Chen-Wei Chen; Chung-Hui Chen; M.-H. Liao

</tex-math></inline-formula>), material thicknesses (<inline-formula> <tex-math notation=LaTeX>


International Journal of Heat and Mass Transfer | 2013

The novel chamber hardware design to improve the thin film deposition quality in both 12″ (300 mm) and 18″ (450 mm) wafers with the development of 3D full chamber modeling and experimental visual technique

M.-H. Liao; Chih-Hua Chen; Ssu Chieh Kao

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International Journal of Automation and Smart Technology | 2015

A non-linear analytic stress model for the analysis on the stress interaction between TSVs

M.-H. Liao; Ssu-Chieh Kao; Sung-Jie Huang

</tex-math></inline-formula>), and impurity concentrations (<inline-formula> <tex-math notation=LaTeX>


Procedia Engineering | 2014

Stress and Curvature of Periodic Trench Structures on Sapphire Substrate with GaN Film

Cho-Fan Hsieh; Chen-Wei Chen; Chung-Hui Chen; M.-H. Liao

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Archive | 2014

The Improving Si0.5Ge0.5/Si Interface Quality through a Low Energy Hydrogen Plasma Cleaning Process and Positron Annihilation Spectroscopy

Cho-Fan Hsieh; Chen-Wei Chen; Chih-Hua Chen; M.-H. Liao

</tex-math></inline-formula>) are studied by thermoelectric measurements and developed simulation model for the study of self-heating effect. With the input of these module-level material properties in our developed finite-element model, the self-heating effect on the CMOS logic transistors from 20- to 5-nm technology nodes are investigated systematically and accurately. The maximum chip temperature in the 14/16-nm technology node Si FinFET device is ~170 °C. On the other hand, the higher operated temperature is also observed in high mobility material devices such as Ge and III-V (InAs) FinFETs due to their poor material properties of <inline-formula> <tex-math notation=LaTeX>

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Cho-Fan Hsieh

Industrial Technology Research Institute

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Chen-Wei Chen

Industrial Technology Research Institute

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Chih-Hua Chen

National Taiwan University

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Ssu Chieh Kao

National Taiwan University

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Chih Hua Chen

National Taiwan University

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Chung-Hui Chen

National Taiwan University

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Li Cheng Chang

National Taiwan University

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C.-P. Hsieh

National Taiwan University

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Chang-Chun Lee

Chung Yuan Christian University

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Chen Yang

National Taiwan University

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