M.-H. Liao
National Taiwan University
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Publication
Featured researches published by M.-H. Liao.
IEEE Transactions on Electron Devices | 2012
M.-H. Liao; Chih Hua Chen; Li Cheng Chang; Chen Yang; Ssu Chieh Kao
Based on the stress extraction and measurement by the atomic-force-microscope-Raman technique with nanometer-level space resolution, the high compressive stress about 700 MPa on the Si critical dimension (CD) is observed in the current complementary metal-oxide-semiconductor (CMOS) transistor. The difference of thermal expansion between Si and Shallow trench isolation (STI) oxide during the total thermal budget for the standard CMOS transistor manufacture process results in this high compressive stress in Si CD and will further degrade the electron carrier mobility about 25% seriously. In order to relax this intrinsic-processed compressive stress in Si CD and recover this device performance loss, the novel process is proposed in this paper in addition to the usage of one-side pad-SiN layer demonstrated in our previous work. With this novel process of additional nitrogen-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress in the Si CD can be achieved by the smaller difference of thermal expansion coefficients between Si and highly n-doped SiO2 STI oxide. The formation of Si-N bonding in the STI-oxide region can be monitored by Fourier-transform infrared spectroscopy spectra, and the thermal expansion coefficients for Si, SiO2, and SiN are 2.6, 0.4, and 2.87 ppm/K, respectively. The relaxation of intrinsic-processed compressive stress in the Si CD of about 400 MPa by this proposed additional nitrogen IMP treatment contributes 14 % electron-carrier-mobility enhancement/recovery. The experimental electrical data agree well with the theoretical k.p calculation for the strained-Si theory.
IEEE Transactions on Electron Devices | 2017
M.-H. Liao; C.-P. Hsieh; Chang-Chun Lee
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IEEE Transactions on Electron Devices | 2015
M.-H. Liao; Chih Hua Chen; Li Cheng Chang; Chih-Wei Yang; Ssu Chieh Kao
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IEEE Transactions on Electron Devices | 2013
Chih Hua Chen; M.-H. Liao; Li Cheng Chang; Ssu Chieh Kao; M.-Y. Yu; G.-H. Liu; Meng-Chi Huang
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2012 International Silicon-Germanium Technology and Device Meeting (ISTDM) | 2012
M.-H. Liao; You-Yin Chen; Chung-Hui Chen; Li-Te Chang; Czau-Siung Yang; C.-F. Hsieh
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Procedia Engineering | 2014
Cho-Fan Hsieh; Chen-Wei Chen; Chung-Hui Chen; M.-H. Liao
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International Journal of Heat and Mass Transfer | 2013
M.-H. Liao; Chih-Hua Chen; Ssu Chieh Kao
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International Journal of Automation and Smart Technology | 2015
M.-H. Liao; Ssu-Chieh Kao; Sung-Jie Huang
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Procedia Engineering | 2014
Cho-Fan Hsieh; Chen-Wei Chen; Chung-Hui Chen; M.-H. Liao
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Archive | 2014
Cho-Fan Hsieh; Chen-Wei Chen; Chih-Hua Chen; M.-H. Liao
</tex-math></inline-formula>) are studied by thermoelectric measurements and developed simulation model for the study of self-heating effect. With the input of these module-level material properties in our developed finite-element model, the self-heating effect on the CMOS logic transistors from 20- to 5-nm technology nodes are investigated systematically and accurately. The maximum chip temperature in the 14/16-nm technology node Si FinFET device is ~170 °C. On the other hand, the higher operated temperature is also observed in high mobility material devices such as Ge and III-V (InAs) FinFETs due to their poor material properties of <inline-formula> <tex-math notation=LaTeX>