Chang-Chun Lee

Current crowding-induced electromigration in SnAg3.0Cu0.5 microbumps

To determine the relevance of current crowding to electromigration in the SnAg3.0Cu0.5 solder bump, a three-dimensional dual bumps simulation model was designed to demonstrate how current crowding can enhance the local atomic flux along the electron flow path. The finding of void formation occurred at the entrance points to the cathode sides and the enhancement of the growth and clustering of the intermetallic compound at the outgoing points of the anode sides along the electron flow path were verified experimentally. The tilting effect is obvious at the anode/chip side. The experimental mean-time-to-failure was observed, and Black’s equation with Joule heating effect were investigated as well.

Thermal–mechanical behavior of the bonding wire for a power module subjected to the power cycling test

Abstract Two analytical methods were proposed in this research, coupled electro-thermal finite element (FE) analysis and thermal–mechanical FE analysis, to analyze the mechanical behavior of bonding wire of power module under cyclic power loads, and the International Electrotechnical Commission standard is adopted in conducting a power cycling test. The exterior temperature distribution was measured by an infrared thermometer. Moreover, the junction temperature is calculated from the given thermal impedance of the semiconductor chip, chip power loss, and case temperature. Subsequently, the simulated temperature distribution via electro-thermal FE analysis is compared with experimental results to validate the methodology used in the aforementioned analysis. The analysis shows compressive stress at the wire/chip interface due to CTE mismatch between the aluminum and the chip. Moreover, the major driving force contributing to the shear stress at the interface is the self-expansion of the wire bump.

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity.

Solder joints layout design and reliability enhancement of wafer level packaging

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mm/spl times/10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach are applied to predict standoff heights and geometry profiles of the solder joints. In additions, a hybrid-pad-shape (HPS) system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints is effectively reduced. As a result the solder joint fatigue life under thermal loading is greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, super CSP and fine pitch BGA.

Interfacial Fracture Investigation of Low-k Packaging Using J-Integral Methodology

In order to resolve the issues of RC time delay and high power consumption, IC chips with Cu/low-k interconnects are developed to meet the foregoing requirements. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper metal and the low-k dielectric material as a result of poor adhesion and lower fracture toughness, which results from the inherent mechanical imperfection of low-k materials. This fracturing problem is one of the most urgent issues for the thermomechanical reliability of Cu/low-k interconnects, and it needs to be resolved urgently. For this reason, we propose a prediction methodology of finite-element analysis (FEA) based on J-integral value estimation to investigate the interfacial fracture opportunity of low-k packages. However, the J-integral calculation is path dependent and so crucial in FEA for a crack on an interface between dissimilar materials. Therefore, various paths with an integral contour surrounding the crack tip are considered to avoid a misunderstanding of the cracking energy. All the analytic results indicate that a rectangular contour with a proper ratio of length/width, and multilayers of element close to the delaminating surfaces, is suggested for obtaining a stable J-integral value. On the other hand, the proposed methodology has been validated by a four-point bending test and compared with the relative experimental data of multi-low-k dielectric films. Moreover, under a reliable integral contour path that crack driving force predicted using the type of interfacial crack constructed by means of the element death technique, it shows good agreement with the simulated results of embedding actual crack.

Development of robust flexible OLED encapsulations using simulated estimations and experimental validations

This work analyses the overall stress/strain characteristic of flexible encapsulations with organic light-emitting diode (OLED) devices. A robust methodology composed of a mechanical model of multi-thin film under bending loads and related stress simulations based on nonlinear finite element analysis (FEA) is proposed, and validated to be more reliable compared with related experimental data. With various geometrical combinations of cover plate, stacked thin films and plastic substrate, the position of the neutral axis (NA) plate, which is regarded as a key design parameter to minimize stress impact for the concerned OLED devices, is acquired using the present methodology. The results point out that both the thickness and mechanical properties of the cover plate help in determining the NA location. In addition, several concave and convex radii are applied to examine the reliable mechanical tolerance and to provide an insight into the estimated reliability of foldable OLED encapsulations.

Interfacial Fracture Analysis of CMOS Cu/Low-

The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.

k

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (μ-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <; 50 μm at the outermost region of the packaging structure without μ-bumps significantly reduces approximately 2 μm of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF.

BEOL Interconnect in Advanced Packaging Structures

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10mmtimes10mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA

Development of Cu/Ni/SnAg Microbump Bonding Processes for Thin Chip-on-Chip Packages Via Wafer-Level Underfill Film

ZnO-doped lithium niobate crystals with a doped concentration of up to 8.3mol% were grown by the Czochralski technique. The effects of incorporating Zn2+ ions into LiNbO3 crystals were studied by powder x-ray diffraction and taking polarization hysteresis loop measurements. When the Li-site vacancy model is adopted, the coercive fields obtained from the polarization reversal measurement depend strongly on the number of NbLi4−+4VLi−. However, the coercive field of Zn-doped ions into LiNbO3 is insensitive to the ZnLi2++VLi−. Experimental results indicate that four distinct substitutions of Zn−2 ions incorporated into ions into LiNbO3 crystals for doping concentrations from 0to8.3mol%. The extent of Zn substitution is quantitatively determined for doping of below 7.5mol%.