M. Jech

Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs

Using our physics-based model for hot-carrier degradation (HCD), we analyze the temperature behavior of HCD in nMOSFETs with a channel length of 44 nm. It was observed that, contrary to most previous findings, the linear drain current change (AId,lin) measured during hot-carrier stress in these devices appears to be lower at higher temperatures. However, the difference between the AId,lin values obtained at different temperatures decreases as the stress voltage increases. This trend is attributed to the single-carrier process of Si-H bond rupture, which is enhanced by the electron-electron scattering. We also consider another important modeling aspect, namely, the vibrational life-time of the Si-H bond, which also depends on the temperature. We finally show that our HCD model can successfully capture the temperature behavior of HCD with physically reasonable parameters.

Efficient physical defect model applied to PBTI in high-κ stacks

Instabilities in MOS-based devices with various substrates ranging from Si, SiGe, IIIV to 2D channel materials, can be explained by defect levels in the dielectrics and non-radiative multi-phonon (NMP) barriers. However, recent results obtained on single defects have demonstrated that they can show a highly complex behaviour since they can transform between various states. As a consequence, detailed physical models are complicated and computationally expensive. As will be shown here, as long as only lifetime predictions for an ensemble of defects is needed, considerable simplifications are possible. We present and validate an oxide defect model that captures the essence of full physical models while reducing the complexity substantially. We apply this model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal. Furthermore, we corroborate the simulated defect bands with prior defect-centric studies and perform lifetime projections.

Comphy — A compact-physics framework for unified modeling of BTI

Abstract Metal-oxide-semiconductor (MOS) devices are affected by generation, transformation, and charging of oxide and interface defects. Despite 50 years of research, the defect structures and the generation mechanisms are not fully understood. Most light has been shed onto the charging mechanisms of pre-existing oxide defects by using the non-radiative multi-phonon theory. In this work we present how the gist of physical models for pre-existing oxide defects can be efficiently abstracted at a minimal loss of physical foundation and accuracy. Together with a semi-empirical model for the generation and transformation of defects we establish a reaction-limited framework for unified simulation of bias temperature instabilities (BTI). The applications of the framework we present here cover simulation of BTI for negative (NBTI) and positive (PBTI) gate voltages, life time extrapolation, AC stress with arbitrary signals and duty cycles, and gate stack engineering.

On the limits of applicability of drift-diffusion based hot carrier degradation modeling

We study the limits of the applicability of a drift-diffusion (DD) based model for hot-carrier degradation (HCD). In this approach the rigorous but computationally expensive solution of the Boltzmann transport equation is replaced by an analytic expression for the carrier energy distribution function. On the one hand, we already showed that the simplified version of our HCD model is quite successful for LDMOS devices. On the other hand, hot carrier degradation models based on the drift-diffusion and energy transport schemes were shown to fail for planar MOSFETs with gate lengths of 0.5–2.0 µm. To investigate the limits of validity of the DD-based HCD model, we use planar nMOSFETs of an identical topology but with different gate lengths of 2.0, 1.5, and 1.0 µm. We show that, although the model is able to adequately represent the linear and saturation drain current changes in the 2.0 µm transistor, it starts to fail for gate lengths shorter than 1.5 µm and becomes completely inadequate for the 1.0 µm device.

On the temperature behavior of hot-carrier degradation

We show that - in contrast to previous findings - hot-carrier degradation (HCD) in scaled nMOSFETs with a channel length of 44 nm appears to be weaker at elevated temperatures. However, the distance between degradation traces obtained at 25 and 75° C reduces as the stress voltages increase and at a certain voltage the changes of the linear drain current measured at 25 and 75° C are almost identical in the entire stress time window. We apply our physics-based model for hot-carrier degradation to analyze the temperature behavior of this detrimental phenomenon. This behavior is interpreted in terms of competing single- and multiple-carrier processes of Si-H bond dissociation with the corresponding rates having the opposite temperature dependencies. One of the most important aspects relevant to the temperature behavior of HCD is the bond vibrational life-time which decreases with the temperature.

Modeling of hot-carrier degradation in LDMOS devices using a drift-diffusion based approach

We model hot-carrier degradation (HCD) in n- and p-channel LDMOS transistors using an analytic approximation of the carrier energy distribution function (DF). Carrier transport, which is an essential ingredient of our HCD model, is described using the drift-diffusion (DD) method. The analytical DF is used to evaluate the bond-breakage rates. As a reference, we also obtain the DF from the solution of the Boltzmann transport equation using the spherical harmonics expansion (SHE) method. The distribution functions and interface state density profiles computed using the SHE and DD-based approaches are compared. The comparison of the device degradation characteristics simulated by these two approaches with the experimental data shows that the DD-based variant, which is considerably less computationally expensive, provides good accuracy. We, therefore, conclude that the DD-based version is efficient for predictive HCD simulations in LDMOS devices.

Identification of oxide defects in semiconductor devices: A systematic approach linking DFT to rate equations and experimental evidence

Abstract It is well-established that oxide defects adversely affect functionality and reliability of a wide range of microelectronic devices. In semiconductor-insulator systems, insulator defects can capture or emit charge carriers from/to the semiconductor. These defects feature several stable configurations, which may have profound implications for the rates of the charge capture and emission processes. Recently, these complex capture/emission events have been investigated experimentally in considerable detail in Si/SiO2 devices, but their theoretical understanding still remains vague. In this paper we discuss in detail how the capture/emission processes can be simulated using the theoretical methods developed for calculating rates of charge transfer reactions between molecules and in electro-chemistry. By employing this theoretical framework we link the atomistic defect configurations to known trapping model parameters (e.g. trap levels) as well as measured capture/emission times in Si/SiO2 devices. Using density functional theory (DFT) calculations, we investigate possible atomistic configurations for various defects in amorphous (a)-SiO2 implicated in being involved in the degradation of microelectronic devices. These include the oxygen vacancy and hydrogen bridge as well as the recently proposed hydroxyl E ′ center. In order to capture the effects of statistical defect-to-defect variations that are inevitably present in amorphous insulators, we analyze a large ensemble of defects both experimentally and theoretically. This large-scale investigation allows us to prioritize the candidates from our defect list based on their trap parameter distributions. For example, we can rule out the E ′ center as a possible candidate. In addition, we establish realistic ranges for the trap parameters, which are useful for model calibration and increase the credibility of simulation results by avoiding artificial solutions. Furthermore, we address the effect of nuclear tunneling, which is involved according to the theory of charge transfer reactions. Based on our DFT results, we demonstrate the impact of nuclear tunneling on the capture/emission process, including their temperature and field dependence, and also give estimates for this effect in Si/SiO2 devices.

The impact of mixed negative bias temperature instability and hot carrier stress on single oxide defects

Even though transistors are rarely subjected to idealized bias temperature instability or hot carrier stress conditions in circuits, there is only a limited number of studies available on mixed bias temperature instability and hot carrier stress. Here we summarize the results of the first study of mixed negative bias temperature instability and hot carrier stress (drain stress voltage |VstrD|> 0 V and gate stress voltage |VstrD| ≥ |VDD|) at the single oxide defect level in nano-scale SiON pMOSFETs. We found that less defects contribute to a threshold voltage shift ΔVth during recovery and thus to the recoverable degradation than would be expected from a simple electrostatic model. Time-dependent defect spectroscopy measurements show that even defects at the source side of the oxide can remain neutral after mixed negative bias temperature instability and hot carrier stress although they are fully charged after homogeneous negative bias temperature instability stress. As a consequence, they do not contribute to a ΔVth drift after mixed negative bias temperature instability and hot carrier stress. We show that this unexpected reduction in the defects occupancy can be consistently explained by non-equilibrium processes induced by the large drain voltage such as impact ionization.

Physical modeling of the hysteresis in M0S2 transistors

The hysteresis in the gate transfer characteristics of transistors made of two-dimensional materials is one of the most obvious problems of this novel technology. Here we attempt for the first time to develop a physical modeling approach for describing this hysteresis in devices based on two-dimensional materials. Our model is based on a drift-diffusion TCAD simulation coupled to a previously established non-radiative multiphonon model for describing charge capture and emission events in the surrounding dielectrics, which are considered the main cause for the observed hysteresis. We validate our model against measurement data on a back-gated single-layer MoS2 transistor with SiO2 as a gate dielectric. Our study provides new insights into the physical reasons for the observed hysteresis, thereby leading the way towards an alleviation of this problem in future devices.

On the effect of interface traps on the carrier distribution function during hot-carrier degradation

We study the effect of interface states, generated during hot-carrier stress, on the carrier energy distribution functions (DFs) and check whether this effect perturbs the results of our hot-carrier degradation model. These studies are performed using SiON nMOSFETs with a gate length of 65 nm as exemplary devices. We carry out simulations with different values of the spatially uniform interface state density (Nit) as well as with a coordinate dependent Nit evaluated for real stress conditions. In both cases, the effect of Nit on carrier distribution functions appears to be strong. As for the degradation characteristics, we show that Nit profiles computed with perturbed distribution functions can be substantially different from those obtained with non-perturbed DFs, especially at long stress times. The same trend is visible also for changes in the linear drain current. Additional simulations performed for operating conditions with and without the effect of Nit show that if this effect is not taken into account, this leads to severe underestimation of the device life-time.