G. Rzepa

Long-Term Stability and Reliability of Black Phosphorus Field-Effect Transistors

Black phosphorus has been recently suggested as a very promising material for use in 2D field-effect transistors. However, due to its poor stability under ambient conditions, this material has not yet received as much attention as for instance MoS2. We show that the recently demonstrated Al2O3 encapsulation leads to highly stable devices. In particular, we report our long-term study on highly stable black phosphorus field-effect transistors, which show stable device characteristics for at least eight months. This high stability allows us to perform a detailed analysis of their reliability with respect to hysteresis as well as the arguably most important reliability issue in silicon technologies, the bias-temperature instability. We find that the hysteresis in these transistors depends strongly on the sweep rate and temperature. Moreover, the hysteresis dynamics in our devices are reproducible over a long time, which underlines their high reliability. Also, by using detailed physical models for oxide traps developed for Si technologies, we are able to capture the channel electrostatics of the black phosphorus FETs and determine the position of the defect energy band. Finally, we demonstrate that both hysteresis and bias-temperature instabilities are due to thermally activated charge trapping/detrapping by oxide traps and can be reduced if the device is covered by Teflon-AF.

The role of charge trapping in MoS2/SiO2 and MoS2/hBN field-effect transistors

The commonly observed hysteresis in the transfer characteristics of MoS2 transistors is typically associated with charge traps in the gate insulator. Since in Si technologies such traps can lead to severe reliability issues, we perform a combined study of both the hysteresis as well as the arguably most important reliability issue, the bias-temperature instability. We use single-layer MoS2 FETs with SiO2 and hBN insulators and demonstrate that both phenomena are indeed due to traps in the gate insulator with time constants distributed over wide timescales, where the faster ones lead to hysteresis and the slower ones to bias-temperature instabilities. Our data show that the use of hBN as a gate insulator considerably reduces the number of accessible slow traps and thus improves the reliability. However, the reliability of hBN insulators deteriorates with increasing temperature due to the thermally activated nature of charge trapping.

Gate-sided hydrogen release as the origin of "permanent" NBTI degradation: From single defects to lifetimes

The negative bias temperature instability (NBTI) in pMOS transistors is typically assumed to consist of a recoverable (R) and a so-called permanent (P) component. While R has been studied in great detail, the investigation of P is much more difficult due to the large time constants involved and the fact that P is almost always obscured by R. As such, it is not really clear how to measure P and whether it will in the end dominate device lifetime. We address these questions by introducing a pragmatic definition of P, which allows us to collect long-term data on both large and nanoscale devices. Our results suggest that (i) P is considerably smaller than R, (ii) that P is dominated by oxide rather than interface traps and therefore (iii) shows a very similar bias dependence as R, and finally (iv) that P is unlikely to dominate device lifetime. We argue that a hydrogen-release mechanism from the gate-side of the oxide, which has been suspected to cause reliability problems for a long time [1-6], is consistent with our data. Based on these results as well as our density-functional-theory (DFT) calculations we suggest a microscopic model to project the results to operating conditions.

The “permanent” component of NBTI revisited: Saturation, degradation-reversal, and annealing

While the defects constituting the recoverable component R of NBTI have been very well analyzed recently, the slower defects forming the more “permanent” component P are much less understood. Using a pragmatic definition for P, we study the evolution of P at elevated temperatures in the range 200°C to 350°C to accelerate these very slow processes. We demonstrate for the first time that P not only clearly saturates, with the saturation value depending on the gate bias, but also that the degradation at constant gate bias can also slowly reverse. Furthermore, at temperatures higher than about 300° C, a significant amount of additional defects is created, which are primarily uncharged around Vth but contribute strongly to P at higher VG. Our new data are consistent with our recently suggested hydrogen release model which will be studied in detail using newly acquired long-term data.

Physical modeling of NB TI: From individual defects to devices

Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.

NBTI modeling in analog circuits and its application to long-term aging simulations

We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negative-bias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URL Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.

Microscopic oxide defects causing BTI, RTN, and SILC on high-k FinFETs

Reliability issues of MOSFETs such as bias temperature instability (BTI), random telegraph noise (RTN), and stress-induced leakage current (SILC), are linked to the trapping of charges in oxides. Even though the chemical structure of these oxide defects is still the subject of debate, detailed studies of these reliability phenomena have shown that their physical behavior can be successfully described by non-radiative multi-phonon (NMP) theory. In this work we characterize and study a pMOS high-k FinFET technology starting from degradation measurements up to the simulation of the energy barriers in the framework of NMP theory. This allows to investigate the aforementioned reliability issues all based on their common cause, the microscopic oxide defects.

Efficient physical defect model applied to PBTI in high-κ stacks

Instabilities in MOS-based devices with various substrates ranging from Si, SiGe, IIIV to 2D channel materials, can be explained by defect levels in the dielectrics and non-radiative multi-phonon (NMP) barriers. However, recent results obtained on single defects have demonstrated that they can show a highly complex behaviour since they can transform between various states. As a consequence, detailed physical models are complicated and computationally expensive. As will be shown here, as long as only lifetime predictions for an ensemble of defects is needed, considerable simplifications are possible. We present and validate an oxide defect model that captures the essence of full physical models while reducing the complexity substantially. We apply this model to investigate the improvement in positive bias temperature instabilities due to a reliability anneal. Furthermore, we corroborate the simulated defect bands with prior defect-centric studies and perform lifetime projections.

Complete extraction of defect bands responsible for instabilities in n and pFinFETs

Bias temperature instabilities (BTI) are serious reliability issues in high-k technologies and occur for positive and negative stress voltages in both n and pMOSFETs. The cases with the strongest degradation, namely negative BTI (NBTI) in pMOS and positive BTI (PBTI) in nMOSFETs, are typically studied and modeled separately, which led to considerable inconsistencies regarding the distributions of the responsible defects. Here we present the first study which successfully describes all four combinations of BTI in n/pMOSFETs within a single model. This was achieved by determining the physical properties of the defects in HfO2 and in SiO2. Using our extraction method, any ambiguity regarding the location of the defect bands is completely eliminated, allowing for correct physics-based extrapolation of degradation data to use conditions.

Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI

In the course of years, several models have been put forward to explain noise phenomena, bias temperature instability (BTI), and gate leakage currents amongst other reliability issues. Mostly, these models have been developed independently and without considering that they may be caused by the same physical phenomenon. However, new experimental techniques have emerged, which are capable of studying these reliability issue on a microscopic level. One of them is the time-dependent defect spectroscopy (TDDS). Its intensive use has led to several interesting findings, including the fact that the recoverable component of BTI is due to reaction-limited processes. As a consequence, a quite detailed picture of the processes governing BTI has emerged. Interestingly, this picture has also been found to match the observations made for other reliability issues, such as random telegraph noise, 1/f noise, as well as gate leakage currents. Furthermore, the findings based on TDDS have lead to the development of capture/emission time (CET) maps, which can be used to understand the dynamic response of the defects given their widely distributed parameters.