M.L. Anido

Interactive Ray Tracing on Reconfigurable SIMD MorphoSys

MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A straightforward mechanism is used to handle irregularity among parallel rays in BSP. To support this mechanism, a special data structure is established, in which no intermediate data has to be saved. Moreover, optimizations such as object reordering and merging are facilitated. Data starvation is avoided by overlapping data transfer with intensive computation so that applications with different complexity can be managed efficiently. Since MorphoSys is small in size and power efficient, we demonstrate that MorphoSys is an economic platform for 3D animation applications on portable devices.

Interactive ray tracing using a SIMD reconfigurable architecture

This paper presents an architecture for running interactive ray tracing applications on portable devices such as cell phones, PDAs, and head mounted displays and discusses the main issues related to the mapping of this graphics algorithm using fixed-point arithmetic. The paper shows that a floating-point arithmetic unit, with its associated power and area consumption, can be avoided by using appropriate fixed-point arithmetic and block floating-point operations. It is also shown that a computation intensive graphics method like ray tracing can be used to generate simple images at interactive rates on portable devices. This can be achieved by employing a reconfigurable SIMD architecture on a chip, which trades parallelism for frequency of operation, thus providing significant benefits in power saving, which is essential in portable devices.

Improving the operation autonomy of SIMD processing elements by using guarded instructions and pseudo branches

This paper presents a novel method for improving the operation autonomy of the processing elements (PE) of SIMD-like machines. By combining guarded instructions and pseudo branches it is possible to achieve higher operation autonomy and higher instruction level parallelism than in previous SIMD/ASIMD architectures. The paper shows that it is feasible to avoid most branches and it is also possible to emulate conditional execution on the processing elements, either by using guarded instructions or by using pseudo branches, thus avoiding unnecessary intervention by the array control unit in data-dependant computations. Pseudo branches are used when it is not possible to use guarded instructions. Additionally, they also support the implementation of complex nested if-then-else constructs, improving the execution of irregular dataparallel applications. The paper also shows that the simplicity of the method allows it to be implemented both in fine-grain and coarse-grain SIMD/ASIMD architectures because it does not require significant additional silicon area. Finally, it is shown that pseudo branches can be used to control the power saving of those processing elements that have instructions nullified.

Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures

This paper presents a new technique to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The data scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.

A Novel Predication Scheme for a SIMD System-on-Chip

This paper presents a novel predication scheme that was applied to a SIMD system-on-chip. This approach was devised by improving and combining the unrestricted predication model and the guarded execution model. It is shown that significant execution autonomy is added to the SIMD processing elements and that the code size is reduced considerably. Finally, the implemented predication scheme is compared with predication schemes of general purpose processors, and it is shown that it enables more efficient if-conversion compilations than previous architectures.

A tool for test automation with support for remote tests

This paper presents an interactive MS-Windows(R)-based framework for high-level specification and analysis of tests on printed circuit boards, using the IEEE 1149.1 standard, and also on integrated circuits using scan design like the LSSD testing methodology. As novel contributions we provide an object-oriented tool for Boundary Scan and LSSD test automation with support for remote tests, including interfaces to circuit description, chip interconnection, test vector analysis and test vector generation. The system includes features like remote testing (using client-server technology), project management, menu-based command entry, user-defined configuration and a comprehensive set of commands.

TEDMOS-a CAD system for ASIC design on IBM-PC like computers

The TEDMOS computer aided design (CAD) system is described and it comprises a suitable system for application specific integrated circuit (ASIC) design on IBM PC like computers. The paper discusses the main assets and shortcomings of TEDMOS, when compared with other CAD systems, and presents its architecture. Emphasis is placed on both a software overview and on the algorithms. Particular attention is paid to hierarchical design, fast circuit simulation, and the hardware limitations imposed by IBM PC like machines.<<ETX>>

Interactive ray tracing on reconfigurable SIMD MorphoSys

MorphoSys is a reconfigurable SIMD architecture. In this paper, a BSP-based ray tracing is gracefully mapped onto MorphoSys. The mapping highly exploits ray-tracing parallelism. A straightforward mechanism is used to handle irregularity among parallel rays in BSP. To support this mechanism, a special data structure is established, in which no intermediate data has to be saved. Moreover, optimizations such as object reordering and merging are facilitated. Data starvation is avoided by overlapping data transfer with intensive computation so that applications with different complexity can be managed efficiently. Since MorphoSys is small in size and power efficient, we demonstrate that MorphoSys is an economic platform for 3D animation applications on portable devices.

A novel method for improving the operation autonomy of SIMD processing elements

A novel method for improving the operation autonomy of the processing elements (PE) of SIMD-like machines is presented and discussed in this paper. The paper shows that it is feasible to avoid most branches and it is also possible to emulate nested if-then-else sentences on the processing elements by combining guarded instructions and pseudo branches. This prevents unnecessary intervention by the array control unit in many data-dependant computations, particularly those with short branch sections. The paper also shows that the simplicity of the method allows it to be implemented both in fine-grain and coarse-grain SIMD/ASIMD architectures because it does not require significant additional silicon area. Finally, it is shown that pseudo branches can be used to control the power saving of those processing elements that have instructions nullified.

Developing a distributed architecture for design rule checking

This paper describes the design and implementation of a distributed object-oriented design rule checker (DRC). The main focus is on the methodology employed to implement this distributed application. Code reusability is achieved using an OO approach, making objects available for other tools, such as circuit extractor. The paper also addresses the application of design patterns, which produce loosely coupled elements, facilitating the integration of system modules.