M. Le Helley

Simulation of electrothermal interactions in power integrated circuits

The authors present SETIPIC, a software package which couples electric and thermal simulations to forecast the electrothermal interactions in the first design steps of power integrated circuits. To give a consistent interface to the designer, SETIPIC is integrated in the EDGE CAD system PICMOST, the thermal simulator used by SETIPIC to obtain the thermal distribution on the layout surface in a transient or stationary mode, is also described. It takes into account the chip environment by the connection of different thermal networks, and uses an automatic mesh method to handle the layout configurations. An infrared experimental method is described to characterize the thermal distribution on a chip. This system was used to validate PICMOST. Some simulation results are given.<<ETX>>

Design automation of power integrated circuits in EDGE environment

Presents SETIPIC, a software package to forecast the electrothermal interactions in the first design steps of power integrated circuits. To give a well-consistent interface with graphic tools to the designer, SETIPIC works under the EDGE CAD system. The software aspect of this integration into EDGE is explained. PICMOST, the thermal simulator used by SETIPIC to obtain the thermal distribution on the layout surface in a transient or stationary mode is also described. In particular, the method to take into account the chip environment (package...) with an automatic mesh to handle aleatory layout configurations is explained. Finally, some thermal simulation results are given.<<ETX>>

Layout automation of CMOS analog building blocks with CADENCE

Presents a set of tools for aiding to the design of analog CMOS circuits. The procedures described can generate automatically the layout of CMOS cells. In addition to the electrical parameters of each component, transistor, resistors, capacitors, the designer can give a shape description which will be used for placement and routing. The layout is generated with respect to specified design rules. The procedures have been written in SKILL language. SKILL is a trademark of CADENCE.<<ETX>>

SETIPIC: electrothermal simulator for power integrated circuits in EDGE environment

The authors present SETIPIC, a software to simulate the electrothermal interactions in the first design steps of power integrated circuits. To give a well-consistent interface to the designer, SETIPIC has been integrated in the EDGE CAD system. The software aspect of this integration is explained. SETIPIC works around SPICE3 (electric simulation) and PICMOST (thermal simulation). This thermal simulator which calculates the thermal distribution on the layout surface of a chip taken in its environment is also described. Finally, an infrared experimental set up is proposed to validate SETIPIC and some thermal and electrothermal simulation results are given.<<ETX>>

Using a CMOS ASIC technology for the development of an integrated ISFET sensor

To take advantage of microelectronics, attempts have been made to integrate sensors in silicon and furthermore to accommodate the whole system formed of the sensor and its signal processing circuit. The major problem is the compatibility between both processes: elaboration of the sensor and integration of the measurement circuit. In this paper the authors present a method allowing industrial production of integrated ISFET sensor. An ASIC CMOS line is used to integrate the signal processing circuit; then the sensor is fabricated by a specific process that does not alter the function of the circuit.<<ETX>>

Dedicated processor for partial differential equation solver

A hardware solver for Delta Psi =f( Psi ), by the finite-difference method in 3D is presented. The general architecture is given: several identical processors run in a parallel mode in a PC-type environment. Each processor is a specific circuit (ASIC). The arithmetic unit has been integrated in a CMOS 2 mu m technology. Using this circuit to simulate potential distribution in silicon devices shows a drastic reduction of the computation time, 1.7 mu s per discretization node against 900 mu s by a software approach.<<ETX>>

Experimental multiprocessor architecture dedicated for solving 3D PDEs

In order to achieve more accurate studies, there is a definite trend towards 3D numerical simulations, which require very long computation times. We report on a parallel architecture multiprocessor system dedicated to the resolution of 3D partial differential equations (PDEs), to be linked to a classical workstation. This parallel system improves the calculation times mainly by use of spatial parallelism. Some examples of resolutions by means of a finite volume discretisation method are presented, as well as an interesting approach using the scanning order of the discretisation nodes.<<ETX>>

Determination of potential at the beveled interface between two materials

Abstract A numerical method is described to compute the electrostatic potential at the beveled interface between two different materials by solving the two-dimensional Poissons equation. The bevel angles are discretized in such a manner that an exact expression for the normal component of the electric field can be used. Curved interfaces can be treated. This method has been employed to calculate the potential distribution in a power VMOS device.