M. Mohiuddin

Elimination of Current Blocking in Ternary InAlAs-InGaAs-InAlAs Double Heterojunction Bipolar Transistors

Molecular beam epitaxy-grown wafers are used to fabricate all ternary In_0.52Al_0.48As-In_0.53Ga_0.47As-In_0.52Al_0.48As double heterojunction bipolar transistors (DHBTs) with knee voltages of less than 1 V, showing no current blocking characteristic even at current densities of 200 kA/cm². A set of wafers with a judicious combination of doping interface dipoles and composite collector designs were grown, and devices with a wide range of emitter areas from 20 × 20 down to 1 × 5 μm² were fabricated to investigate the effects of the different epitaxial and geometrical design tradeoffs that culminated in an optimum design that is able to achieve high breakdown and high current gain without introducing current blocking. Despite the use of a heavy dipole doping of 4 × 10¹⁸ cm^-3, a breakdown voltage BV_CEO of 5.8 V at 0.2 kA/cm² is achieved at room temperature. We believe this to be the first demonstration of an all-ternary large band gap InAlAs-InGaAs-InAlAs DHBTs with no current blocking up to a high current density of 200 kA/cm². These new DHBTs that use only ternary alloys may lead to simplified device growth and fabrication options and give deeper understanding of the design tradeoffs in these structures.

2-D Physical Modelling of 6-doped GaAs/AlGaAs HEMT

GaAs/AIGaAs is one the most prevalent material systems for high electron mobility transistors (HEMTs) especially at very low temperatures because of its very high mobility under these conditions. In this work, full physical modelling of a GaAs/AIGaAs HEMT with 1 mum gate length geometry is presented. The model is developed using 2-D ATLAS SILVACO[f] simulator and compared with measurements obtained from a similar HEMT fabricated at the University of Manchester using molecular beam epitaxy (MBE). Models taking into account the effect of transverse and lateral electric fields on mobility, deep-level traps, Fermi-level pinning, carrier generation/recombination and tunnelling have been included and these have led to excellent agreements between modelled and experimental values. The mobility model used has the largest effect on simulated I-V curves and inclusion of deep-level traps in the AlGaAs buffer layer improved the model considerably by raising carrier confinement in the channel.

GHz Class Low-Power Flash ADC for Broadband Communications

A low-power (~400 mW) high-speed (2-4 GS/s) 4-bit analogue-to-digital converter (ADC) based on InP/InGaAs heterojunction bipolar transistors (HBT) has been designed and simulated. The technology utilised two novel developments. Firstly stoichiometric conditions permitted growth at a relatively low temperature (420degC) while conserving extremely high-quality materials. Secondly dimeric phosphorus generated from a gallium phosphide (GaP) decomposition source has lead to excellent device properties. The complete ADC shows state-of-the-art performance and includes an interface for connection to standard digital signal processing (DSP) systems whilst dissipating only 400 mW.

Temperature studies of InAlAs-InGaAs-InAlAs double heterojunction bipolar transistors with no current blocking

In this paper, elimination of current blocking for the temperature range 77 K to 400 K is experimentally demonstrated for all ternary InAlAs–InGaAs–InAlAs double heterojunction bipolar transistors of emitter area 100 × 100 µm2. The wafers were grown by molecular beam epitaxy without using any complex growth techniques such as coherent heterointerfaces for reflection and penetration superlattice or quaternary alloys for grading. A room temperature breakdown (BVceo) of 5 V is achieved despite the collector thickness of less than 2000 A and heavy dipole doping of 4 × 1018 cm−3. Activation energies calculated from the Gummel plots indicate the shift of the transport mechanism across the junction from thermionic emission to predominantly tunneling as the temperature is lowered to 77 K.

RAMAN STUDIES OF DELTA-DOPED SEMICONDUCTORS AND QUANTUM WELLS

Theoretical and experimental studies of the Raman spectra of delta-doped bulk GaAs and GaAs–AlxGa1−xAs multiple quantum wells are presented. Intersubband plasmon modes are calculated with an energy-dependent effective-mass theory, which takes into account the band nonparabolicity. The screened external potential due to impurity and electron charge distribution including the exchange and correlation effects are calculated self consistently within the local density approximation. The calculated Raman spectra are in agreement with experimental data with a reasonable assumption of doping profile.

Physical Modelling of the Kink Effect in Strained InGaAs/InAlAs pHEMTs

The InAlAs/InGaAs material system provides one of the highest transconductance pHEMT devices at a given gate size because of its large conduction band discontinuity, high electron mobility and very good carrier confinement in the channel. The DC characteristics, however, show a sudden rise in drain current at fixed value of drain voltage, resulting in high drain conductance and reduced voltage gain. This undesirable phenomenon is called Kink Effect. In this work a comprehensive understanding of the causes of this effect is developed using a 2-D physical device simulator. The modelled pHEMT is a layered structure that simulates the epitaxial layers of the fabricated device grown by MBE[1]. The developed model takes into account field dependent mobility, generation recombination mechanisms and deep-level traps are used. With the help of these physical models, threshold voltage, drain saturation and gate leakage current are successfully simulated and agree well with the measured results.

Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm

Simulated Annealing (SA) algorithm is widely employed to achieve optimal placement solution for FPGAs. However, it attempts a notably large number of placement moves on each temperature step, thus increasing the placement runtime considerably. The work presented in this paper reduces the placement runtime by intelligently reducing the total number of placement moves attempted on each temperature step. We have proposed four alternate formulas for calculating the number of moves that must be attempted per temperature step. Empirical study shows that our proposed formulas have achieved up to 2.1 times reduction in placement runtime without compromising placement quality.

Study of Switching and Kirk Effects in InAlAs/InGaAs/InAlAs Double Heterojunction Bipolar Transistors

This paper investigates the two dominant but intertwined current blocking mechanisms of Switching and Kirk Effect in pure ternary InAlAs/InGaAs/InAlAs Double Heterojunction Bipolar Transistors (DHBTs). Molecular Beam Epitaxy (MBE) grown, lattice-matched samples have been investigated giving substantial experimental results and theoretical reasoning to explain the interplay between these two effects as the current density is increased up to and beyond the theoretical Kirk Effect limit for devices of emitter areas varying from 20x20 μm 2 to 1x5 μm 2 . Pure ternary InAlAs/InGaAs/InAlAs DHBTs are ideally suited for such investigations because, unless corrective measures are taken, these devices suffer from appreciable current blocking effect due to their large conduction band discontinuity of 0.5 eV and thus facilitating the observation of the two different physical phenomena. This enhanced understanding of the interplay between the Kirk and Switching effect makes the DHBT device design and optimization process more effective and efficient.

Low temperature performance of pure ternary InAlAs-InGaAs-InAlAs double heterojunction bipolar microwave transistors

All ternary InAlAs-InGaAs-InAlAs Double Heterojunction Bipolar Transistors (DHBTs) are experimentally demonstrated to operate down to liquid nitrogen temperature with a breakdown (BVceo) voltage of 7.6 V at 0.05 kA/cm2 which is achieved despite collector thickness of only 2000 Å and heavy dipole doping of 4 × 1018 cm−3. The wafers were Molecular Beam Epitaxy grown without resorting to any complex growth techniques such as CHIRP (coherent heterointerfaces for reflection and penetration) superlattice or quaternary alloys for grading. Gummel plot shows a finite current gain varying from 4 to 30, as collector current was varied over six orders of magnitude (from 7 nA to 7 mA), and up to a current density of 50 kA/cm2 at 77 K. The resulted high breakdown voltage and relatively better current gain stability over temperature in comparison with SiGe make these microwave devices of relaxed geometry (1 × 15) µm2, fabricated using simple optical lithography which are suitable for many low temperature applications such as high-sensitivity cooled sensors and detectors and cryogenic low-noise amplifiers (LNAs) offering a competitive alternative to deep-submicron SiGe technology.

Low-power LVDS driver using InP HBT ECL circuits for SKA

Indium phosphide Heterojunction Bipolar Transistors (HBTs)-based, low power, Low Voltage Differential Signalling (LVDS) driver to interface digital circuits operating at varied logic levels is designed using Emitter Coupled Logic (ECL) circuits operating at 2 GHz clock speed. The core of the ECL circuit is based on a voltage to current converter/buffer. The total power dissipation of the driver with LVDS compatible output levels is less than 15mW. This is achieved with a relaxed geometry of 5 × 5μm2 area HBT devices fabricated on Molecular Beam Epitaxy (MBE) grown wafers. The circuit makes use of dynamic switching of output transistors without using any complex circuitry, which reduces total power consumption without appreciably compromising on speed or area. These results are better than those reported on 0.35 μm CMOS technology and is comparable with designs built on 0.35 μm BICMOS technology.