M. P. Scott

Reduction in misfit dislocation density by the selective growth of Si1−xGex/Si in small areas

Si1−xGex and Si layers have been grown selectively in the exposed Si regions on oxide‐patterned 〈100〉 oriented Si wafers using the chemical vapor deposition technique limited reaction processing. Misfit dislocation spacings at the heterointerface were measured using plan‐view transmission electron microscopy in conjunction with a large‐area thinning technique which allows for examination of 100–150 μm diameter areas. The dislocation density is reduced by at least a factor of 20 for small areas (lateral dimensions: tens of microns) bounded by oxide isolation when compared to adjacent large areas (millimeters) which are uninterrupted by the patterned oxide. The ability to selectively grow Si1−xGex on patterned wafers and the area‐dependent reduction in dislocation density in as‐grown films may be important considerations for future device applications using Si1−xGex strained layers.

Low dislocation density, large diameter, liquid encapsulated Czochralski growth of GaAs

Abstract We have grown 70 nm diameter, 1200 g, 〈100〉 oriented GaAs single crystals in a low thermal gradient environment. Without intentional doping we have obtained average KOH etch pit densities (EPD) of 5000 cm -2 over 70% of the wafer area, and throughout 75% of the ingot length. This material is semi-insulating with a resistivity of 2 × 10 7 Ω cm. By doping with Si to give free carrier concentrations in the range of 1 to 5 × 10 18 cm -3 , we reproducibly obtain average EPDs of -2 . Near the bottom of the ingot, wafers are virtually dislocation free except very near the wafer edge. The distribution of etch pits across the wafer is in general agreement with the thermoelastic stress model: high at the edges and in the center, but with an annular region essentially dislocation free (Si-doped). The axial distribution, however, does not fit this model: generally high at the seed and tail ends of the crystal and low through the bulk of the ingot. Transmission X-ray topographs confirm the nature and extent of the dislocation distribution.

Limited reaction processing: Growth of Si1−xGex/Si for heterojunction bipolar transistor applications

Abstract Limited reaction processing (LRP) of silicon-based materials is reviewed as an alternative growth method to molecular beam epitaxy (MBE). LRP is a chemical vapor deposition technique which uses wafer temperature, rather than gas flow switching, to initiate and terminate growth. Processing takes place within a cold-wall, quartz reaction chamber, and gases are changed between successive lamp-heated growth cycles. In addition to minimizing thermal exposure, the technique allows individual layers in a multi-layer structure to be deposited at their optimum growth temperature. LRP is particularly well suited to the growth and processing of metastable layers such as strained Si 1− x Ge x on silicon. Several properties of LRP-grown Si 1− x Ge x are shown to be similar to those reported for MBE material, including qualitative islanding behavior and quantitative measurement of the onset of misfit dislocation formation. However, a direct comparison of thermal stability reveals larger numbers of misfit dislocations in MBE-grown films upon annealing. The electrical behavior of misfit dislocations in heterojunction diodes, and the growth and analysis of high-quality Si/Si 1− x Ge x /Si heterojunction bipolar transistors are also discussed.

Junction leakage in titanium self‐aligned silicide devices

Successful utilization of a titanium self‐aligned silicide (salicide) process for reproducible device fabrication with high yield requires junction leakage due to the silicide process to be minimized. The microstructure and microchemistry of titanium salicide shallow junction diodes were studied and correlated with junction leakage. The direct correlation between junction leakage and junction structure was established by using several analytical techniques. The main cause of large leakage current was found to be a loss of p+/n junction under the titanium silicide layer and formation of titanium silicide/n‐silicon Schottky barrier contact at the perimeter of the diodes. Process parameters for low leakage titanium silicide/p+/n diode fabrication were also established.

Thermal stability of Si/Si1−xGex/Si heterojunction bipolar transistor structures grown by limited reaction processing

The thermal stability of Si/500‐A‐thick Si0.77Ge0.23 bilayers grown on Si by limited reaction processing is studied as a function of Si capping layer thickness. After annealing for 4 min at 850 °C, misfit dislocation spacings increase monotonically with cap thickness from 0.5 μm for an uncapped film to greater than 50 μm for a layer with a 500‐A‐thick cap. Thus, an epitaxial Si cap of sufficient thickness prevents significant misfit dislocation formation during this anneal. Experimental observations are reported which indicate that the Si cap enhances thermal stability by inhibiting both dislocation nucleation and propagation. These results are very encouraging since they suggest that high‐temperature processing of Si/Si1−xGex device structures may be possible without significant misfit dislocation formation.

Silicon and indium doping of GaAs: Measurements of the effect of doping on mechanical behavior and relation with dislocation formation

Abstract The effect of indium and silicon doping on dislocation formation in GaAs single crystals has been studied experimentally using dynamic compression tests and indentation rosettes. By direct measurements of the critical resolved shear stress (CRSS) in temperature range from 400 to 1100° C using dynamic compression tests, we found that at the melting point, the critical resolved shear stress of GaAs: In is twice that of undoped GaAs. More recent measurements show that at high temperatures (T ⩾ 1000° C) the critical resolved shear stress of silicon-doped crystals is lower than that of undoped GaAs. Well-defined indentation rosettes were obtained at high temperatures from a Vickers indenter using small loads. Analysis of such rosettes confirm that the mechanical behavior of the GaAs crystals is not drastically affected by the presence of dopants. Reduction of dislocation densities in doped crystals is attributed to modifications introduced by the dopant in the equilibrium concentration of native defects at the melting point (particularly gallium and arsenic vacancies).

The effect of oxygen on the thermal stability of Si1−xGex strained layers

The thermal stability of Si1−xGex strained layers containing 2×1020 oxygen atoms/cm3 is compared with that of similar layers (same Ge fraction and film thickness) containing more than two orders of magnitude less oxygen. For the layers with high oxygen levels, no misfit dislocations were found in films as thick as two times the theoretical equilibrium critical thickness, after annealing at 850 °C for 4 min. In contrast, dislocations were found in the layers with low oxygen levels at thicknesses very near the equilibrium critical thickness after the same anneal. X‐ray measurements of lattice constants in high and low oxygen films of similar Ge content indicate that oxygen does not substantially change the amount of strain in the layers. Oxygen appears to impede the kinetics of dislocation formation.

Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors fabricated by limited reaction processing

The DC performance of Si/Si/sub 1-x/Ge heterojunction bipolar transistors (HBTs) fabricated from epitaxial layers grown by limited reaction processing is presented. The highest gain ( approximately=400) device has a 20-nm, 31%-Ge base heavily doped with boron to a level of 7*10/sup 18/ cm/sup -3/. Measurements of the collector current as a function of temperature yield values of the valence band discontinuity, Delta E/sub v/, for four different Ge compositions. The dependence of Delta E/sub v/ on Si/sub 1-x/Ge/sub x/ layer thickness was also measured and found to decrease as strain relaxation occurred.<<ETX>>

Microscopic identification of defects propagating through the center of silicon and indium‐doped liquid encapsulated Czochralski grown GaAs using x‐ray topography

Extended defects in 3×1018 cm−3 Si‐doped and 2×1019 cm−3 In‐doped GaAs grown by the liquid encapsulated Czochralski technique are investigated using x‐ray topography and found to include straight and helicoidal dislocations propagating along the central axis of the ingot. These dislocations are not simply extensions of dislocations in the seed. The defect morphology is explained by strong interaction with native point defects and elastic strain associated with solute segregation at the growing interface.

High frequency Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors

Small-geometry, high-performance Si-Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors have been fabricated using chemical vapor deposition to form the epitaxial device layers and direct-write, electron-beam lithography. The measured value of f/sub T/ is approximately 29 GHz. Base-collector capacitance is one of the dominant limiting parasitic parameters in the mesa structure used to demonstrate high-speed performance. Advanced epitaxial techniques, such as selective deposition of Si/sub 1-x/Ge/sub x/, should reduce this parasitic element significantly, markedly increasing device speed. Selective deposition of Si/sub 1-x/Ge/sub x/ has been demonstrated.<<ETX>>