M. Postranecky

The data acquisition and calibration system for the ATLAS Semiconductor Tracker

The SemiConductor Tracker (SCT) data acquisition (DAQ) system will calibrate, configure, and control the approximately six million front-end channels of the ATLAS silicon strip detector. It will provide a synchronized bunch-crossing clock to the front-end modules, communicate first-level triggers to the front-end chips, and transfer information about hit strips to the ATLAS high-level trigger system. The system has been used extensively for calibration and quality assurance during SCT barrel and endcap assembly and for performance confirmation tests after transport of the barrels and endcaps to CERN. Operating in data-taking mode, the DAQ has recorded nearly twenty million synchronously-triggered events during commissioning tests including almost a million cosmic ray triggered events. In this paper we describe the components of the data acquisition system, discuss its operation in calibration and data-taking modes and present some detector performance results from these tests

Design and development of electronics for the EuXFEL clock and control system

The development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module (RTM). Each RTM controls up to 16 Front End Modules (FEMs) for a 1 Megapixel 2D detector. The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors.

Further development of the MTCA.4 clock and control system for the EuXFEL megapixel detectors

The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to evaluate the system functionality such as Front End Electronics (FEE) communication and the performance metrics such as the FEE clock jitter. The final version of the CC hardware along with the associated firmware are also presented.