M. Warren

The data acquisition and calibration system for the ATLAS Semiconductor Tracker

The SemiConductor Tracker (SCT) data acquisition (DAQ) system will calibrate, configure, and control the approximately six million front-end channels of the ATLAS silicon strip detector. It will provide a synchronized bunch-crossing clock to the front-end modules, communicate first-level triggers to the front-end chips, and transfer information about hit strips to the ATLAS high-level trigger system. The system has been used extensively for calibration and quality assurance during SCT barrel and endcap assembly and for performance confirmation tests after transport of the barrels and endcaps to CERN. Operating in data-taking mode, the DAQ has recorded nearly twenty million synchronously-triggered events during commissioning tests including almost a million cosmic ray triggered events. In this paper we describe the components of the data acquisition system, discuss its operation in calibration and data-taking modes and present some detector performance results from these tests

Charge collection studies in irradiated HV-CMOS particle detectors

Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

A double-sided, shield-less stave prototype for the ATLAS Upgrade strip tracker for the High Luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools.

Design and development of electronics for the EuXFEL clock and control system

The development of the Clock and Control (CC) hardware and firmware for the EuXFEL DAQ system is presented. The system exploits the data handling advances provided by the new telecommunication architecture standard for physics. The CC is responsible for synchronising the DAQ system to overall system timing. The hardware consists of a DESY designed MTCA.4 board and a UCL designed Rear Transition Module (RTM). Each RTM controls up to 16 Front End Modules (FEMs) for a 1 Megapixel 2D detector. The CC system is designed to provide extendibility and scalability to support future upgrades to the DAQ or larger detectors.

Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with the AMS H35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in the High-Luminosity LHC

The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.

Further development of the MTCA.4 clock and control system for the EuXFEL megapixel detectors

The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to evaluate the system functionality such as Front End Electronics (FEE) communication and the performance metrics such as the FEE clock jitter. The final version of the CC hardware along with the associated firmware are also presented.

Investigations into the impact of locally modified sensor architectures on the detection efficiency of silicon micro-strip sensors

The High Luminosity Upgrade of the LHC will require the replacement of the Inner Detector of ATLAS with the Inner Tracker (ITk) in order to cope with higher radiation levels and higher track densities. Prototype silicon strip detector modules are currently developed and their performance is studied in both particle test beams and X-ray beams. In previous test beam measurements of prototype modules, the response of silicon sensors has been studied in detailed scans across individual sensor strips. These scans found instances of sensor strips collecting charge across areas on the sensor deviating from the geometrical width of a sensor strip. The variations have been linked to local features of the sensor architecture. This paper presents results of detailed sensor measurements in both X-ray and particle beams investigating the impact of sensor features (metal pads and p-stops) on the sensor strip response.

Characterisation of strip silicon detectors for the ATLAS Phase-II Upgrade with a micro-focused X-ray beam

The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 61034 cm−2s−1. A consequence of this increased luminosity is the expected radiation damage at 3000 fb−1 after ten years of operation, requiring the tracking detectors to withstand fluences to over 11016 1 MeV neq/cm2. In order to cope with the consequent increased readout rates, a complete re-design of the current ATLAS Inner Detector (ID) is being developed as the Inner Tracker (ITk).Two proposed detectors for the ATLAS strip tracker region of the ITk were characterized at the Diamond Light Source with a 3 μm FWHM 15 keV micro focused X-ray beam. The devices under test were a 320 μm thick silicon stereo (Barrel) ATLAS12 strip mini sensor wire bonded to a 130 nm CMOS binary readout chip (ABC130) and a 320 μm thick full size radial (end-cap) strip sensor - utilizing bi-metal readout layers - wire bonded to 250 nm CMOS binary readout chips (ABCN-25).A resolution better than the inter strip pitch of the 74.5 μm strips was achieved for both detectors. The effect of the p-stop diffusion layers between strips was investigated in detail for the wire bond pad regions.Inter strip charge collection measurements indicate that the effective width of the strip on the silicon sensors is determined by p-stop regions between the strips rather than the strip pitch.

The CHESS-2 prototype in AMS 0.35 μm process: A high voltage CMOS monolithic sensor for ATLAS upgrade

CHESS-2 (CMOS HV Evaluation for Strip Sensors) is a novel ASIC strip architecture designed to investigate the feasibility of using HV-CMOS MAPS (Monolithic Active Pixel Sensors) as alternative sensors for the ATLAS Phase-II Strip Tracker Upgrade. The ASIC is optimized for signal processing, hit pixel position encoding and readout. CHESS-2 includes three independent groups of 128 strips composed of 32 pixels each. The pixel includes a charge sensitive amplifier and the first stage of a comparator inside the collecting well. The second stage, the configuration, the encoding and the readout sections are placed at the periphery of the strips. A novel “fast skip” hit encoding logic identifies the first 8 hit pixel positions with a single-bunch time resolution (25 ns) and sends the data to a fast readout circuitry for serialization and transmission on 14 LVDS channels at 320 MHz. Several substrate resistivity variants have been fabricated for a full characterization of the performance aspects.