M.R. Pinto

Secondary Electron flash-a high performance, low power flash technology for 0.35 /spl mu/m and below

This work presents recent results on Secondary Electron flash memory, and contrasts this approach to standard for scaled, low power mass storage applications.

EEPROM/flash sub 3.0 V drain-source bias hot carrier writing

Stacked-gate memory devices have been realized which for the first time demonstrate efficient hot carrier writing for drain-source bias, V/sub DS/, down to 2.5 V. Writing is achieved by channel initiated secondary electron injection, which permits writing for qV/sub DS/ below the 3.2 eV oxide barrier. Writing times of 1 ms are achieved for floating gate voltages V/sub FG/ as low as 1.2 V, with V/sub DS/=-V/sub BS/=2.5 V, voltages which can easily be derived from a single scaled power supply, the back-gate bias generated by low-current charge pumping. No high voltage transistors are required for writing or V/sub T/ convergence. Moreover, because the devices are based on a fully scaled 0.25 /spl mu/m CMOS process, NV-memory arrays can be easily integrated with a minimum of additional process steps. Tight V/sub T/ convergence together with low voltage operation and scaling compatibility makes them ideal candidates for Giga-bit Flash.

Explanation of reverse short channel effect by defect gradients

Reverse short channel effect (RSCE), the paradoxical increase in threshold voltage (V/sub t/) of short channel MOSFETs, has previously been explained by diffusion broadening of a buried channel profile. We report here on RSCE in transistors which have very shallow or flat channel profiles, where such broadening cannot be the mechanism. It is shown that for several different dopings and process sequences, both RSCE and anomalous body effects can be traced back to transient enhanced diffusion (TED) of the channel profile induced by source/drain implantation. A new mechanism for RSCE is proposed, in which the surface recombination of interstitials under the gate gives rise to an impurity flux to the surface, which raises the threshold. A coupled defect/impurity diffusion model allows all short channel effects on threshold to be accurately predicted.<<ETX>>

Elimination of heterojunction band discontinuities by modulation doping

Heterojunction band discontinuities have been an active field of research during the last decade’ and made possible the realization of new device concepts such as modulation-doped transistors, heterobipolar transistors, and quantum-well lasers. The physical principles of these devices are based on heterojunction band discontinuities. In other device structures, however, heterojunction band discontinuities impede the flow of charge carriers across the junction. These structures include the optical distributed Bragg reflector which consists of alternating layers of two semiconductors with different refractive index, each having a thickness of a quarter wavelength. If distributed Bragg reflectors are used for current conduction, the constituent heterojunction band discontinuities impede the current flow, which is a highly undesired concomitant effect. It is the purpose of this publication to demonstrate that unipolar heterojunction band discontinuities can be eliminated by modulation doping and compositional grading of heterojunctions. The charge carrier transport across a heterojunction is illustrated in Fig. 1, which shows the band diagram of two semiconductors “A” and “B.” Band discontinuities occur in the conduction and valence band since the fundamental gap of semiconductor B is larger than the gap of A. Such discontinuities are usually referred to as type-1 heterojunctions, which contrast to type-11 (staggered) and type-III (broken gap) heterostructures. Transport across the heterojunction barrier can occur via thermal emission or via tunneling as schematically illustrated in Fig. 1. For sufficiently thick and high barriers, tunneling and thermal emission of carriers are not efficient transport mechanisms across the barrier. It is therefore desirable to eliminate such heterojunction band discontinuities in the conduction or valence band. Modulation doping of a parabolically graded heterojunction will next be shown to result in a flat-band-edge potential. The band diagram of a parabolically graded conduction-band edge is shown in Fig. 2 (a). The energy of the band edge increases parabolically with a positive second derivative between the points z, and z,. The band edge further increases parabolically with a negative second derivative between z2 and zs. The energy of the band edge can be expressed as / -&(z,) + 2(zf~z,)‘iz - zd’

Monte Carlo simulation of the CHISEL flash memory cell

This work shows how physically-based hot carrier simulation was used to understand the importance of CHannel Initiated Secondary ELectron (CHISEL) injection in scaled MOSFETs, and how it was used to develop a powerful CHISEL-based technique for low voltage flash programming. Furthermore, it is shown how CHISEL flash addresses many of the disadvantages of CHE programming techniques, making it an ideal candidate for low-voltage, low-power Gigabit flash memories.

Silicon MOS transconductance scaling into the overshoot regime

Simulations incorporating velocity overshoot are used to derive the dependence of deep-submicrometer MOS transconductance on low-field mobility mu /sub eff/ and channel length L/sub ch/. In contract to strict velocity saturation, saturated transconductance departs from a strict mu /sub eff//L/sub ch/ dependence when overshoot is considered. Constraints on mu /sub eff/ derived from conventional scaling laws together with strong mu /sub eff/ dependencies in these regimes indicate the importance of low-field inversion layer control and optimization. Transconductance in saturation is shown to approach a well-defined limit for very high mu /sub eff/.<<ETX>>

Charge injection logic

The charge injection transistor is a semiconductor device based on transfer of hot electrons between separately contacted conducting layers. The nature of hot‐electron injection by the real‐space transfer allows the implementation of novel circuit elements. In particular, we propose a multiterminal single‐device structure that works as a functional element with three logic inputs Xj (j=1,2,3) and one output equal to (X1∩X2∩X3)∪(X1∩X2∩X3). This device, called the norand, can perform both as a nor(X1,X2) and as an and(X1,X2) element, reprogrammable electrically by changing the X3 input. The operation of norand with logic gain is demonstrated experimentally by an equivalent circuit connection of discrete charge injection transistors implemented within InGaAs/InAlAs on InP technology.

Scaling the Si metal‐oxide‐semiconductor field‐effect transistor into the 0.1‐μm regime using vertical doping engineering

Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon‐on‐insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.

High performance 0.1- mu m room temperature Si MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>

Two-dimensional numerical analysis of latchup in a VLSI CMOS technology

The latchup behavior of a VLSI CMOS technology using hybrid Schottky-ohmic contact sources and drains and a high resistivity substrate has been extensively studied via two dimensional numerical simulation. The modeling allows quantitative explanation of the triggering and sustaining behavior of such structures, as well as an accurate characterization of the influence of the various process and geometrical parameters on the resistance to latchup. The technology is compared to a corresponding low resistivity substrate (epi) CMOS technology.