Robert W. Dutton

A charge-oriented model for MOS transistor capacitances

A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribution in the device rather than from capacitances. The effective capacitances which result are nonreciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.

VLSI Process modeling—SUPREM III

Over the past several years, the process-simulation tool SUPREM II has proven useful in the design and optimization of both bipolar and MOS technologies. This paper describes a new and significantly more capable version of the program--SUPREM III--which incorporates process models suitable for VLSI device design. This new version of the program is now generally available and should provide a powerful new tool in VLSI design. For the first time, the program models multilayer structures (up to five material layers). It also incorporates substantially upgraded diffusion, oxidation, ion implantation, and other process models. These models incorporate, where possible, recent thinking about underlying physical mechanisms. The program remains a one-dimensional simulator; extensions to two dimensions are discussed. This paper concentrates on the process models and their underlying physics; implementation issues are addressed elsewhere.

An improved energy transport model including nonparabolicity and non-Maxwellian distribution effects

An improved energy transport model for device simulation is derived from the zeroth and second moments of the Boltzmann transport equation (BTE) and from the presumed functional form of the even part of the carrier distribution in momentum space. Energy-band nonparabolicity and non-Maxwellian distribution effects are included to first order. The model is amenable to an efficient self-consistent discretization taking advantage of the similarity between current and energy flow equations. Numerical results for ballistic diodes and MOSFETs are presented. Typical spurious velocity overshoot spikes, obtained in conventional hydrodynamic (HD) simulations of ballistic diodes, are virtually eliminated.<<ETX>>

Nonplanar VLSI device analysis using the solution of Poisson's equation

Techniques are presented for calculating the drain current of small-geometry MOSFETs in the linear, subthreshold, and punch-through regions of device operation. The current calculation depends only on the electrostatic solution of the two-dimensional Poisson equation in the device. The accuracy of the techniques is established by comparisons with full two-dimensional simulations based on the simultaneous solution of the Poisson and minority-carrier current-continuity equations. The results of simulation also agree well with measurements on MOSFETs having submicrometer effective channel lengths. The application of the simulations to nonplanar technologies is illustrated by the analysis of a taper-isolated dynamic-gain RAM cell. A description is given of simple numerical techniques for solving Poissons equation in the presence of nonplanar boundaries. The solution method demonstrates good convergence characteristics and minimizes computer storage requirements. Consequently, the simulation capabilities have been successfully implemented on a desktop calculator (Hewlett-Packard 9845) and on minicomputers (Hewlett-Packard 2100 and 1000-F).

A noise optimization technique for integrated low-noise amplifiers

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

Kinetics of thermal nitridation processes in the study of dopant diffusion mechanisms in silicon

The changes in diffusion rates of Sb, As, and P resulting from nitridation of SiO2 and direct nitridation of the silicon surface in NH3 ambient at 1100 °C are studied for times ranging from 7 min to 4.5 h. From analysis of these data we conclude that P must diffuse almost entirely by an interstitialcy mechanism at this temperature, and that previous formulations of dopant diffusion under nonequilibrium conditions may not be complete. We also determine that the effects seen during direct nitridation are better explained by a pure vacancy injection process than a pure self‐interstitial depletion process, contrary to previous assertions by us and others.

Comprehensive study of noise processes in electrode electrolyte interfaces

A general circuit model is derived for the electrical noise of electrode–electrolyte systems, with emphasis on its implications for electrochemical sensors. The noise power spectral densities associated with all noise sources introduced in the model are also analytically calculated. Current and voltage fluctuations in typical electrode–electrolyte systems are demonstrated to originate from either thermal equilibrium noise created by conductors, or nonequilibrium excess noise caused by charge transfer processes produced by electrochemical interactions. The power spectral density of the thermal equilibrium noise is predicted using the fluctuation-dissipation theorem of thermodynamics, while the excess noise is assessed in view of charge transfer kinetics, along with mass transfer processes in the electrode proximity. The presented noise model not only explains previously reported noise spectral densities such as thermal noise in sensing electrodes, shot noise in electrochemical batteries, and 1/f noise in corrosive interfaces, it also provides design-oriented insight into the fabrication of low-noise micro- and nanoelectrochemical sensors.

Impact of gate direct tunneling current on circuit performance: a simulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.

Characterization of contact electromechanics through capacitance-voltage measurements and simulations

Electrostatically actuated polysilicon beams fabricated in the multiuser MEMS process (MUMPs) are studied, with an emphasis on the behavior when the beam is in contact with an underlying silicon nitride dielectric layer. Detailed two-dimensional (2-D) electromechanical simulations, including the mechanical effects of stepups, stress-stiffening and contact, as well as the electrical effects of fringing fields and finite beam thickness, are performed. Comparisons are made to quasi-2-D and three-dimensional simulations. Pull-in voltage and capacitance-voltage measurements together with 2-D simulations are used to extract material properties. The electromechanical system is used to monitor charge buildup in the nitride which is modeled by a charge trapping model. Surface effects are included in the simulation using a compressible-contact-surface model. Monte Carlo simulations reveal the limits of simulation accuracy due to the limited resolution of input parameters.

Transient Analysis of MOS Transistors

Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numerical and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping, The validity and limits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.